Abstract: Provided are a driving simulator apparatus and a driver rehabilitation training method using the apparatus, the apparatus including: a display unit for displaying a preset simulation driving screen; a mode selecting unit via which a normal mode, an assist mode, or a resist mode is selected by a user; and a control unit for controlling to apply a driving force in a rotational direction of a steering wheel operated by a user when the assist mode is selected and to apply a reaction in an opposite direction to the rotational direction of the steering wheel operated by the user when the resist mode is selected.

Abstract: A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract: A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adjacent to one another and define memory block pairs. The flash memory device can further include a row selection circuit that is configured to drive the word lines responsive to memory operations associated with a memory address, where the row selection circuit can include respective shield lines that are located between the memory blocks included in each pair and each of the memory blocks in the pair has a common source line therebetween.

Abstract: A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract: A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at intersections of word lines and bit lines, where ones of the plurality of memory blocks are immediately adjacent to one another and define memory block pairs. The flash memory device can further include a row selection circuit that is configured to drive the word lines responsive to memory operations associated with a memory address, where the row selection circuit can include respective shield lines that are located between the memory blocks included in each pair and each of the memory blocks in the pair has a common source line therebetween.

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.