Abstract: A redundancy circuit selectively drives two or more redundancy memory cell arrays to improve the integration of a highly integrated semiconductor memory device. To do this, the redundancy circuit has at least two memory blocks, each having a plurality of normal memory cell arrays and a redundancy memory cell array for replacing a defective memory cell array, at least two redundancy cell array drivers respectively connected to at least two redundancy memory cell arrays for driving at least two redundancy memory cell arrays, a defective-cell-array detection fuse box for detecting address corresponding to a defective memory cell array, and a driving controller for driving one of at least two redundancy cell array drivers by outputs of the defective-cell-array detection fuse box and the block selection fuse box.

Abstract: A semiconductor memory device having an improved data transmission circuit reduces voltage swing width of data to be transmitted from a plurality of memory cells to an output buffer, so as to improve data reading speed.