Abstract: The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

Abstract: A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks.

Abstract: A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal and first down signal and the quadrant decision unit may determine the phase location for the current output clock and output quadrant decision signals based on a phase location. The quadrant controller may output a second up signal and a second down signal based on the first up signal and the first down signal and the quadrant decision signals, and the charge pump unit may output a first and second phase control voltage based on the second up signal and the second down signal. The phase interpolator may select clocks from a plurality of clocks based on the quadrant decision signals and output an output clock signal based on the selected clocks.

Abstract: A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks.

Abstract: The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.