Patents by Inventor Hwa Weng Koh

Hwa Weng Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY
    Publication number: 20130034954
    Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
    Type: Application
    Filed: October 8, 2012
    Publication date: February 7, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
  • Integrated circuit system including nitride layer technology
    Patent number: 8283263
    Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: October 9, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
  • INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY
    Publication number: 20080032513
    Abstract: An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
    Type: Application
    Filed: July 5, 2006
    Publication date: February 7, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
  • Method of forming ultra thin silicon oxynitride for gate dielectric applications
    Patent number: 7202164
    Abstract: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: April 10, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jinping Liu, Hwa Weng Koh, Dong Kyun Sohn, Liang Choo Hsia
  • Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses
    Patent number: 6946349
    Abstract: A method for integrating a SONOS device with an improved top oxide with SiO2 gate oxides of different thickness is described. In a first embodiment during ISSG oxidation to form the SiO2 gate oxides, a thin sacrificial silicon nitride layer is used over the top oxide of the ONO to minimize loss and to control the top oxide thickness. In a second embodiment the top oxide layer for the SONOS device is formed by depositing an NO stack. During ISSG oxidation to form the SiO2 gate oxides a portion of the Si3N4 in the NO stack is converted to SiO2 to form the top oxide with improved thickness control.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: September 20, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jae Gon Lee, Hwa Weng Koh, Elgin Quek, Dong Kyun Sohn