Patents by Inventor Hwai-Pwu Chou

Hwai-Pwu Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8088692
    Abstract: A method for fabricating a multilayer microstructure with balancing residual stress capability includes forming a multilayer microstructure on a silicon substrate and conducting a step of isotropic plasma etching. The multilayer microstructure includes a first metal layer and a second metal layer patterned and aligned symmetrically to form etching through holes; a metal via layer surrounding each etching through hole; and an insulating layer filling each etching through hole and disposed between the substrate and the first metal layer. The step of isotropic chemical plasma etching removes the insulating layer in each etching through hole, the insulating layer between the substrate and the metal layer and a portion of the substrate to form a suspended multilayer microstructure on the substrate, during which a chamber pressure larger than vacuum and maintains a ratio between a lateral etching rate and a vertical etching rate between 0.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: January 3, 2012
    Assignee: National Tsing Hua University
    Inventors: Ying-Jui Huang, Hwai-Pwu Chou
  • Patent number: 7940089
    Abstract: A peak detect-and-hold circuit and method thereof using ramp sampling technique includes utilizing two sampling signals of different slopes to sample an input voltage for respective tracking voltages; comparing the held tracking voltage sampled with the sampling signal of a smaller slope and the input voltage to determine whether the input voltage is rising or falling, and if the input voltage starts falling, the held tracking voltage sampled with the sampling signal of a larger slope is taken as the peak. The peak detect-and-hold circuit using ramp sampling technique controls respective tracking voltages by comparing the input voltage with the sampling signals rather than the feedback tracking voltage. Also, it uses the input voltage directly rather than an operational transconductance amplifier to charge holding capacitors for the tracking voltages. Therefore, the errors of peak detecting and holding, namely the pedestal voltage, overshoot voltage and voltage droop are reduced.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: May 10, 2011
    Assignee: National Tsing Hua University
    Inventors: Hwai-Pwu Chou, Chien-Jen Lin
  • Publication number: 20110057706
    Abstract: A peak detect-and-hold circuit and method thereof using ramp sampling technique includes utilizing two sampling signals of different slopes to sample an input voltage for respective tracking voltages; comparing the held tracking voltage sampled with the sampling signal of a smaller slope and the input voltage to determine whether the input voltage is rising or falling, and if the input voltage starts falling, the held tracking voltage sampled with the sampling signal of a larger slope is taken as the peak. The peak detect-and-hold circuit using ramp sampling technique controls respective tracking voltages by comparing the input voltage with the sampling signals rather than the feedback tracking voltage. Also, it uses the input voltage directly rather than an operational transconductance amplifier to charge holding capacitors for the tracking voltages. Therefore, the errors of peak detecting and holding, namely the pedestal voltage, overshoot voltage and voltage droop are reduced.
    Type: Application
    Filed: October 6, 2009
    Publication date: March 10, 2011
    Inventors: Hwai-Pwu CHOU, Chien-Jen Lin
  • Publication number: 20110008962
    Abstract: A method for fabricating a multilayer microstructure with balancing residual stress capability includes forming a multilayer microstructure on a substrate and conducting a step of isotropic plasma etching. The multilayer microstructure includes a first metal layer, a second metal layer, a metal via layer and an insulating layer. The first metal layer and the second metal layer are patterned and aligned symmetrically so as to form etching through holes. The metal via layer surrounds each etching through hole. The insulating layer fills each etching through hole and is disposed between the substrate and the first metal layer. The step of isotropic chemical plasma etching removes the insulating layer in each etching through hole and the insulating layer between the substrate and the metal layer so as to form a suspended multilayer microstructure on the substrate.
    Type: Application
    Filed: October 8, 2009
    Publication date: January 13, 2011
    Inventors: Ying-Jui HUANG, Hwai-Pwu CHOU