Abstract: A method and apparatus for enhancing a speech signal contaminated by additive noise through Kalman filtering. The speech is decomposed into subband speech signals by a multichannel analysis filter bank including bandpass filters and decimation filters. Each subband speech signal is converted into a sequence of voice frames. A plurality of low-order Kalman filters are respectively applied to filter each of the subband speech signals. The autoregression (AR) parameters which are required for each Kalman filter are estimated frame-by-frame by using a correlation subtraction method to estimate the autocorrelation function and solving the corresponding Yule-Walker equations for each of the subband speech signals, respectively. The filtered subband speech signals are then combined or synthesized by a multichannel synthesis filter bank including interpolation filters and bandpass filters, and the outputs of the multichannel synthesis filter bank are summed in an adder to produce the enhanced fullband speech signal.

Abstract: The present invention provides a sinusoidal transform vocoder based on the Bark spectrum, which has high quality and low bit rate for coding. The present invention includes the steps of transforming a harmonic sine wave from a frequency spectrum to a perception-based Bark spectrum. An equal-loudness pre-emphasis and the loudness to a subjective loudness transformation are also involved in the method. Last, a pulse code modulation (PCM) is used to quantize the subjective loudness to obtain quantized subjective loudness. In synthesis, the Bark spectrum is inversely processed to obtain the excitation pattern following the sone-to-phone conversion and equal-loudness deemphasis. Then, the sine wave amplitudes can be estimated from the excitation pattern by assuming that the amplitudes belonging to the same critical band are equal.

Abstract: A digital artificial neural network (ANN) reduces memory requirements by storing sample transfer function representing output values for multiple nodes. Each nodes receives an input value representing the information to be processed by the network. Additionally, the node determines threshold values indicative of boundaries for application of the sample transfer function for the node. From the input value received, the node generates an intermediate value. Based on the threshold values and the intermediate value, the node determines an output value in accordance with the sample transfer function.

Abstract: A circuit for implementing a neural network comprises a one dimensional systolic array of processing elements controlled by a microprocessor. The one dimensional systolic array can implement weighted sum and radial based type networks including neurons with a variety of different activation functions. Pipelined processing and partitioning is used to optimize data flows in the systolic array. Accordingly, the inventive circuit can implement a variety of neural networks in a very efficient manner.

Abstract: A reconfigurable neural network includes several switches each having at least two conductive leads, data flow direction of the conductive leads is programmed to select one of the conductive leads as input switch lead and select another one of the conductive leads as an output switch lead. Several processing elements each having leads connected to the switches, where the processing elements and the switches are interconnected in one-dimension manner. The neural network of interconnected switches and processing elements has a bit-serial input and a bit-serial output.

Abstract: A reconfigurable neural network is disclosed. The neural network includes a plurality of switches each having at least two conductive leads, wherein data flow direction of the conductive leads of the switches is programmed to select one of the conductive leads as input switch lead and select another one of the conductive leads as an output switch lead. A plurality of processing elements each having a plurality of leads connected to the switches, wherein the processing elements and the switches are interconnected in one-dimension manner. Each of the processing elements comprising: (a) a serial-in-parallel-out accumulator having a first input coupled to one of the interconnected switches and generating a first output; (b) an activation function for transforming the first output of the serial-in-parallel-out accumulator and generating a second output; and (c) a parallel-in-serial-out shift register for shifting out the second output of the activation function serially to one of the interconnected switches.

Abstract: Parallel processing architecture is used for an adder and its "look-ahead" zero-flag generator, which generates a flag signal for the most significant bit of the sum of the adder. The look-ahead zero-flag is generated with combinatorial logic circuits, which are fed from the addends and augents of the different bits for the adder and then decoded. The combinatorial logic circuits may comprise AND gates and XOR gates in a gate-array, and the decoder may be a programmable logic array (PLA). The computation time for the zero-flag thus generated is shorter than the computation time for the sum of the adder.