Abstract: A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.

Abstract: In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

Abstract: A refresh circuit is configured to generate a counting signal by counting a refresh command and to generate a plurality of preliminary refresh cycle change signals by decoding the counting signal. The refresh circuit is also configured to change a refresh cycle based on one of the plurality of preliminary refresh cycle change signals and to perform a refresh operation.

Abstract: A flame-retardant sheet attaching device is disclosed. The flame-retardant sheet attaching device may include a first pressurizing device configured to move in a first direction and apply pressure to a flame-retardant sheet, and a second pressurizing device configured to move in the first direction, the second pressurizing device having at least a portion inserted into a groove of the flame-retardant sheet. The flame-retardant sheet may be configured to move, based on the movement of the second pressurizing device, in a second direction, perpendicular to the first direction. The first pressurizing device may be configured to restrict the movement of the flame-retardant sheet in the first direction, when the flame-retardant sheet moves in the second direction.

Abstract: A Schottky diode includes a semiconductor layer structure that is interposed between first and second contacts. The semiconductor layer structure comprises a current spreading layer having a first conductivity type, a drift region between the second contact and the current spreading layer, the drift region having the first conductivity type, and a first blocking junction having a second conductivity type that is opposite the first conductivity type, the first blocking junction extending downwardly from an upper surface of the semiconductor layer structure. The current spreading layer has a first conductivity type dopant concentration that is at least 1.5 times greater than a first conductivity type dopant concentration of the drift region and the current spreading layer vertically overlaps at least a portion of a lower half of the first blocking junction.

Abstract: A battery device manufacturing system is disclosed. In some embodiments, the battery device manufacturing system includes a plurality of first manufacturing lines configured to manufacture a plurality of battery cells and a cell assembly in which the plurality of battery cells are stacked, a plurality of second manufacturing lines configured to couple a busbar assembly to the cell assembly to manufacture a sub-battery module, and a plurality of third manufacturing lines configured to couple the sub-battery module to a case to manufacture a battery module, wherein one of the plurality of third manufacturing lines is configured to receive the sub-battery module from each of two second manufacturing lines among the plurality of second manufacturing lines.

Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

Abstract: The present disclosure relates to a pixel sensing circuit in which a test is performed only on selected specific channels among channels of the pixel sensing circuit and the total test time of the pixel sensing circuit and data throughput for the test may be reduced.

Abstract: A Schottky diode according to some embodiments includes a silicon carbide drift layer having a first conductivity type, and a junction shielding region in the drift layer. The junction shielding region has a second conductivity type opposite the first conductivity type. The Schottky diode further includes an anode contact on the silicon carbide drift layer. The anode contact includes a refractory metal nitride, and forms a Schottky junction with the drift layer and an ohmic contact to the junction shielding region.

Abstract: In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

Abstract: A semiconductor device includes a semiconductor layer having a first area and an edge termination area outside the first area. The semiconductor layer has a first conductivity type, an active area in the first area, a test area in the first area adjacent the active area, a first anode contact on the semiconductor layer in the active area, a second anode contact on the semiconductor layer in the test area, and a cathode contact in electrical contact with the semiconductor layer. A related method of testing surge current capability of a semiconductor device includes applying a forward current that is smaller than a maximum forward current of the semiconductor device to a test active area that is within an area inside a main edge termination area of the semiconductor device, and detecting a failure of the semiconductor device in response to the forward current.

Abstract: A semiconductor apparatus includes a parity operation circuit, a write latch circuit, a data processing circuit and a write path. The parity operation circuit generates a parity signal by performing an operation on operation source data. The write latch circuit generates a write parity signal by latching the parity signal according to a delayed write signal. The data processing circuit outputs write data as the operation source data in a write operation, and delays the operation source data by a time required for operation of the parity signal and outputs it as delayed data. The write path writes the delay data and the write parity signal to a memory area in the write operation.

Abstract: A semiconductor device includes a semiconductor layer including an active area, a first implanted region within the active area at a surface of the semiconductor layer, and an integrated test area in the semiconductor layer. The integrated test area includes a second implanted region in the semiconductor layer.

Abstract: An optical see-through display apparatus includes an image output module, a display panel, an optical shutter panel to adjust a transmittance of an external light for each of R, G, and B colors. The display apparatus includes an optical sensor to measure a color of the external light. The display apparatus includes a processor that generates R, G, and B shutter data through a first compensation algorithm. The first compensation algorithm is operated to: compare a color of a mixed virtual image with a color of a target mixed virtual image, and when a color difference therebetween is a threshold value or less, designate a transmittance of the optical shutter panel as a candidate transmittance, and select a candidate transmittance implementing the mixed virtual image most similar to the target mixed virtual image, and generate the R, G, and B shutter data corresponding to the selected candidate transmittance.

Abstract: Disclosed are a system for receiving and storing an electronic device, and a method for receiving and storing an electronic device at the time of trading. According to an embodiment of the present invention, a system for receiving and storing an electronic device may include a reception storage box in which an electronic device inserted through an inlet port is moved at a predetermined angle to allow the electronic device to be received and stored.

Abstract: A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

Abstract: A method of forming a semiconductor device comprises forming a first mask that includes a longitudinally-extending first opening that has a first width on a semiconductor layer structure. A spacer is formed on sidewalls of the first mask that are exposed by the first opening to form a second mask, where the first and second masks comprise a mask structure that has a longitudinally-extending second opening that has a second width that is smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure underneath the third opening.

Abstract: A light emitting device is described, which has a first encapsulation film enclosing an outside and a top surface of a light emitting diode. The first encapsulation film comprises an organic thin film of a fluorine-based polymer and an inorganic material infiltrated into a void of the fluorine-based polymer and linked chemically to the fluorine-based polymer. Optionally, a second encapsulation film can be disposed between a substrate and the light emitting diode. The encapsulation film provides a moisture barrier, while being flexible. Since the encapsulation film provides improved barrier properties to moisture and the like, the light emitting device can maintain good current density, luminous efficiency and luminance. The light emitting device can be a display device, a lighting device, a touch screen, etc.

Abstract: Disclosed are a system and method for obtaining device internal information in electronic devices. The system for obtaining device internal information, according to an embodiment of the present invention, may comprise the steps of: receiving a selection for ‘user action before input’ from a user through a UI screen of an automated device; recognizing a product information ID screen displayed on a display of a mobile device put into an input space of the automated device when ‘screen-on state input’ is selected as the ‘user action before input’; and reading a unique ID of the mobile device from the recognized product information ID screen.