Abstract: A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.

Abstract: A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.

Abstract: A chiplet system with an auto-swapping function and a signal communication method thereof are provided. The chiplet system at least includes a first chiplet and a second chiplet. The signal communication method includes the following steps. The first chiplet and the second chiplet are electrified. The first chiplet and the second chiplet are reset and driven. Through a serial number information, the first chiplet and the second chiplet are identified. A handshaking communication procedure is executed by the first chiplet and the second chiplet to confirm whether a pin connection relationship between the first chiplet and the second chiplet is correct. If the pin connection relationship between the first chiplet and the second chiplet is incorrect, pin function switching is performed by the first chiplet or the second chiplet.

Abstract: A semiconductor device package has two integrated circuits. Each of the two integrated circuits has a core circuit and a digital input/output (I/O) interface circuit. The core circuits of the two integrated circuits are powered by two different core voltages, and the I/O circuits of the two integrated circuits are powered by the same core voltage selected from the two different core voltages.

Abstract: A high code-density microcontroller architecture with changeable instruction formats has a memory for storing compressed instructions each including a group prefix and at least one index. An instruction decompressor is provided for decompressing the compressed instructions to be executed into original instructions. The instruction decompressor includes a plurality of instruction group decoding tables, each being stored with the original instructions of a predetermined type. One instruction group decoding table is selected based on the group prefix of the compressed instruction for searching the corresponding original instruction therein by the index of the compressed instruction.

Abstract: A microprocessor structure and a method for implementing digital filter operations are disclosed, which utilize an increment/decrement unit, and an accumulator unit and a register set which are already existing in a microprocessor, to provide finite impulse response digital filter and inner product operations. With the increment/decrement unit, when a finite impulse response digital filter operation is executed, it is able to automatically move the data into a memory, so that when a next operation is executed, it is able to immediately perform the operation simply by writing new data and setting pointers, whereby the microprocessor can efficiently perform the operations of digital signal processing.

Abstract: A memory structure for speeding up data access is disclosed. The memory structure has a row decoder and a column decoder to decode the address in the address bus for addressing the memory cells. A plurality of data latch units, each having at least two latches, are provided to optionally latch the data of the memory cells addressed by the row decoder into one of the latches of each data latch unit. A compare and select logic unit determines whether the data of the memory cells addressed by the row addresses is stored in the plurality of data latch units. If not, one of the latches in each data latch unit is selected for latching the data of the memory cells addressed by the row address. Because data of multiple rows of memory cells can be stored in the data latch units, a high probability exists to have data and instruction code to be accessed stored in the data latch units whereby the speed of memory access is greatly increased.

Abstract: Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.

Abstract: Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.