Abstract: An apparatus for generating an in-phase/quadrature-phase (I/Q) signal in a wireless transceiver is disclosed, including a local oscillator for generating an oscillation signal, and first and second mixers for mixing an oscillation signal with a transmission/reception signal to convert the transmission/reception signal into a baseband or high-frequency signal. The apparatus includes a phase locked circuit for controlling the local oscillator, and a polyphase filter installed between the local oscillator and the mixers, for separating the oscillation signal from the local oscillator into an I signal and a Q signal depending on a control signal from the phase locked circuit, and outputting the separated I and Q signals to the first and second mixers, respectively.

Abstract: Provided is a synchronization apparatus and method for a receiver that performs synchronization in a digital domain and detects a transmission signal. The synchronization apparatus includes an Analog-to-Digital (A/D) converter for converting a received signal into a digital signal, a frequency synchronizer for synchronizing a frequency using the digital signal output from the A/D converter, a signal detection unit for detecting a transmission symbol from a signal synchronized by the frequency synchronizer, and a residual phase detector for compensating for a residual phase of the transmission symbol output from the signal detection unit and outputting the resulting transmission symbol. The frequency synchronizer is capable of accurately and efficiently compensating for a frequency offset by minimizing the time delay caused by subcarrier synchronization using an improved CORDIC algorithm.

Abstract: An apparatus for generating an in-phase/quadrature-phase (I/Q) signal in a wireless transceiver is disclosed, including a local oscillator for generating a local oscillation signal, and first and second mixers for mixing the oscillation signal with a transmission/reception signal to convert the transmission/reception signal into a baseband or high-frequency signal. The apparatus includes a phase locked circuit for controlling the local oscillator, and a polyphase filter installed between the local oscillator and the mixers, for separating the oscillation signal from the local oscillator into an I signal and a Q signal depending on a control signal from the phase locked circuit, and outputting the separated I and Q signals to the first and second mixers, respectively.

Abstract: An apparatus and method are provided for controlling a time deinterleaver for digital audio broadcasting (DAB) that reduces a required minimum memory capacity of a DAB receiver. The method and apparatus generate addresses for writing and reading interleaved data transmitted from a transmitter into/from a deinterleaver memory having a plurality of memory areas associated with a plurality of frames of the interleaved data. The apparatus comprises an encoder for outputting, upon receipt of frame information for a first set of frames, frame information for a second set of frames to write the first set of frames in unused memory areas, allocated for the second set of frames, out of the memory areas of the deinterleaver memory; and a ROM in which bit position information of the memory areas for the frames are written such that the memory areas for the first set of frames should not be overlapped with the memory areas for the second set of frames.

Abstract: An apparatus and method are provided for controlling a time deinterleaver for digital audio broadcasting (DAB) that reduces a required minimum memory capacity of a DAB receiver. The method and apparatus generate addresses for writing and reading interleaved data transmitted from a transmitter into/from a deinterleaver memory having a plurality of memory areas associated with a plurality of frames of the interleaved data. The apparatus comprises an encoder for outputting, upon receipt of frame information for a first set of frames, frame information for a second set of frames to write the first set of frames in unused memory areas, allocated for the second set of frames, out of the memory areas of the deinterleaver memory; and a ROM in which bit position information of the memory areas for the frames are written such that the memory areas for the first set of frames should not be overlapped with the memory areas for the second set of frames.