Patents by Inventor HWAN-SIK LIM
HWAN-SIK LIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9312213Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.Type: GrantFiled: August 29, 2013Date of Patent: April 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon Gi Cho, Young Lyong Kim, Sun-Hee Park, Hwan-Sik Lim
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Patent number: 8928150Abstract: A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.Type: GrantFiled: May 7, 2013Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Moon-Gi Cho, Sun-Hee Park, Hwan-Sik Lim, Yong-Hwan Kwon
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Patent number: 8823172Abstract: A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.Type: GrantFiled: February 7, 2014Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hwan-Sik Lim, Sunwon Kang, Jongho Lee
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Patent number: 8759221Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.Type: GrantFiled: June 24, 2013Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., LtdInventors: Jin-Woo Park, Hwan-Sik Lim, Eunchul Ahn
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Publication number: 20140151877Abstract: A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.Type: ApplicationFiled: February 7, 2014Publication date: June 5, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: HWAN-SIK LIM, Sunwon Kang, Jongho Lee
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Publication number: 20140084457Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.Type: ApplicationFiled: August 29, 2013Publication date: March 27, 2014Inventors: Moon Gi CHO, Young Lyong KIM, Sun-Hee PARK, Hwan-Sik LIM
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Patent number: 8680685Abstract: A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.Type: GrantFiled: May 27, 2010Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hwan-Sik Lim, Sunwon Kang, Jongho Lee
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Publication number: 20140015145Abstract: A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.Type: ApplicationFiled: May 7, 2013Publication date: January 16, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Gi CHO, Sun-Hee PARK, Hwan-Sik LIM, Yong-Hwan KWON
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Publication number: 20130288431Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.Type: ApplicationFiled: June 24, 2013Publication date: October 31, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-Woo PARK, Hwan-Sik LIM, EUNCHUL AHN
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Publication number: 20130256876Abstract: A semiconductor package includes a semiconductor chip having a plurality of contact pads on a surface thereof, a plurality of main bumps on the contact pads, respectively. Each of the plurality of main bumps includes a first pillar layer on one of the contact pads and a first solder layer on the first pillar layer, and the first solder layer includes an upper portion having an overhang portion.Type: ApplicationFiled: January 3, 2013Publication date: October 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ui-hyoung LEE, Moon-gi CHO, Mi-seok PARK, Sun-hee PARK, Hwan-sik LIM, Jin-ho CHOI, Fujisaki ATSUSHI
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Patent number: 8519470Abstract: A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect.Type: GrantFiled: March 31, 2011Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., LtdInventors: Sun-won Kang, Hwan-sik Lim
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Patent number: 8497569Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.Type: GrantFiled: March 8, 2011Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Woo Park, Hwan-Sik Lim, Eunchul Ahn
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Publication number: 20130082090Abstract: Methods of forming connection bumps for semiconductor devices in which rewiring patterns are formed. The method includes preparing a semiconductor substrate on which a pad is partially exposed through a passivation film, forming a seed layer on the pad and passivation film, forming a photoresist pattern including an opening pattern comprising a first opening that exposes a portion of the seed layer on the pad and a second opening that exposes a portion of the seed layer on the passivation film and is separated from the first opening, performing a first electroplating to form filler layers in the opening patterns, performing a second electroplating to form a solder layer on the filler layers, removing the photoresist pattern and performing a reflow process to form a collapsed solder layer that electrically connects the filler layers to each other and a solder bump on the filler layer formed in the second opening.Type: ApplicationFiled: September 13, 2012Publication date: April 4, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-gi CHO, Hwan-sik LIM, Sun-hee PARK
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Publication number: 20130009286Abstract: A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.Type: ApplicationFiled: May 15, 2012Publication date: January 10, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-lyong Kim, Jong-ho Lee, Moon-gi Cho, Hwan-sik Lim, Sun-hee Park
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METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME
Publication number: 20120129333Abstract: Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening.Type: ApplicationFiled: September 23, 2011Publication date: May 24, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-Young YIM, Eun-Chul AHN, Ui-Hyoung LEE, Moon-Gi CHO, Hwan-Sik LIM -
Publication number: 20110283034Abstract: A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect.Type: ApplicationFiled: March 31, 2011Publication date: November 17, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-won KANG, Hwan-sik LIM
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Publication number: 20110215444Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.Type: ApplicationFiled: March 8, 2011Publication date: September 8, 2011Applicant: Samsung Electronics Co., LtdInventors: Jin-Woo PARK, Hwan-Sik Lim, Eunchul Ahn
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Publication number: 20110095418Abstract: A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.Type: ApplicationFiled: May 27, 2010Publication date: April 28, 2011Inventors: HWAN-SIK LIM, SUNWON KANG, JONGHO LEE