Abstract: A duplex board system comprises two functionally identical processing boards, one of the boards being in an active state and the other being in a stand-by state, each of the boards generating a state signal depicting the state thereof, wherein the stand-by state board succeeds the active state board when the state of the active state board becomes deactivated; and two cancelling units, each coupled between the two boards for receiving the state signal from one of the boards, suppressing a glitch period from the state signal generated at said one of the boards, the glitch period representing an unstable signal level transition of the state signal, and outputting the glitch suppressed state signal to the other board.

Abstract: A bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors. Each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, respectively, and N is smaller than (M+1). The bus architecture includes a bus having N buses, each of the buses coupled to one or more processors of a hierarchy and (N-1) linking means, and each of the linking means for coupling a bus of a hierarchy to a bus of a next hierarchy.

Abstract: A communication node, for use in an inter-processor communication system in an asynchronous transfer mode switching system, provides two independent paths to upper layer switching modules for two duplicated processors, respectively, wherein the path from the processor to the upper layer switching modules includes the communication node, a node switching device, all devices are duplicated and operate by using an active and stand-by scheme, data transmitted is transmitted in the unit of a data packet and the data packet includes an information field, a node address field and a payload type field for representing whether data is switching inforamtion or not. The node comprises two subnodes controlled by the controller for the active and the stand-by processors, respectively. Each subnode has two buffers for storing received data and sending data.

Abstract: An IPC (Inter-Processor Communications) message router for use in routing an IPC message to a node comprises: a memory for storing receive enable signals at addresses therein, each of the addresses being identical to a routing address included in the IPC message, and outputting receive enable signals stored in the addresses corresponding to the routing address; and a converter and sync signal generator for extracting a routing address from a serial IPC message received, converting the serial routing address into a parallel routing address, sending the parallel routing address to the memory, and generating a sync signal, the sync signal being used in selecting a set of receive enable signals.

Abstract: A method of initializing node addresses for use in an electronic switching system comprises the steps of: (a) storing all possible sets of node addresses, each set corresponding to an inter-processor communications configuration, and pointers in a residue of a memory; (b) receiving information on a designated set of node addresses which corresponds to a selected inter-processor communications configuration to be used; (c) locating a pointer corresponding to the designated set of node addresses; and (d) writing each address in the designated set of node addresses onto each corresponding register.

Abstract: A method of initializing a set of node addresses by using an apparatus having a CPU, a ROM and a NVSRAM for use in an electronic switching system comprises the steps of: (a) checking if there is a request to change the set of node addresses; (b) updating the NVSRAM with a new set of node addresses, and then going to step (f) if there is the request at the step (a); (c) checking if a flag in the NVSRAM is set or not when there is no request at the step (a); (d) going to the step (f) if the flag in the NVSRAM is determined to be set at the step (c); (e) copying the node addresses stored in the ROM to the NVSRAM if the flag in the NVSRAM is determined not to be set at the step (c); and (f) copying the set of node addresses stored in the NVSRAM onto the corresponding nodes.

Abstract: An active/stand-by determination method for use in a duplicated system, wherein two elements, one given a priority and the other not given a priority, in the duplicated system operate in an active mode and a stand-by mode alternatively by using an X.sub.-- ACTIVE signal, a S.sub.-- ACTIVE signal, a STATUS signal for each element and a SIDE signal, the method comprising the steps of: a) setting both the elements in the stand-by mode upon power-on; b) checking the X.sub.-- ACTIVE signal and the STATUS signal at both the elements; c) entering into the active mode if it is determined at the step b) that both the X.sub.-- ACTIVE signal and the STATUS signal are "high"; d) remaining in the stand-by mode if it is determined at the step b) that at least one of the X.sub.