Patents by Inventor Hwang Ho Choi
Hwang Ho Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230176112Abstract: A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.Type: ApplicationFiled: October 18, 2022Publication date: June 8, 2023Inventors: Yeon Ho Jung, Jong Wook Kye, Min Woo Kwak, Mi Joung Kim, Chan Wook Park, Do Hoon Byun, Kwan Seong Lee, Jae Ho Lee, Jae Seung Choi, Hwang Ho Choi
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Patent number: 11483000Abstract: An interface circuit includes a first switch element connected to a first power supply node, supplying a first power supply voltage, and an output node, transmitting an output signal, and controlled by a first input signal, a second switch element connected to a second power supply node, supplying a second power supply voltage, lower than the first power supply voltage, and the output node and controlled by a second input signal, different from the first input signal, a first resistor connected between the first power supply node and the first switch element, a second resistor connected between the second power supply node and the second switch element, a first capacitor connected between the first resistor and the first switch element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switch element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the secondType: GrantFiled: January 28, 2021Date of Patent: October 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hwang Ho Choi, Yungeun Nam, Sodam Ju
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Publication number: 20220014195Abstract: An interface circuit includes a first switch element connected to a first power supply node, supplying a first power supply voltage, and an output node, transmitting an output signal, and controlled by a first input signal, a second switch element connected to a second power supply node, supplying a second power supply voltage, lower than the first power supply voltage, and the output node and controlled by a second input signal, different from the first input signal, a first resistor connected between the first power supply node and the first switch element, a second resistor connected between the second power supply node and the second switch element, a first capacitor connected between the first resistor and the first switch element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switch element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the secondType: ApplicationFiled: January 28, 2021Publication date: January 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Hwang Ho CHOI, Yungeun NAM, Sodam JU
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Patent number: 10476510Abstract: A clock and data recovery device associated with a data receiving apparatus, the clock and data recovery device including an oscillator configured to generate a clock signal; and a regulator configured to supply current to the oscillator, the regulator including, a first current source configured to supply a first current to the oscillator, and a second current source configured to supply a second current to the oscillator such that the second current is supplied to the oscillator, after a period of time, to de-emphasize the first current, the period of time being based on the first current.Type: GrantFiled: July 2, 2018Date of Patent: November 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Hwang Ho Choi
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Publication number: 20190173475Abstract: A clock and data recovery device associated with a data receiving apparatus, the clock and data recovery device including an oscillator configured to generate a clock signal; and a regulator configured to supply current to the oscillator, the regulator including, a first current source configured to supply a first current to the oscillator, and a second current source configured to supply a second current to the oscillator such that the second current is supplied to the oscillator, after a period of time, to de-emphasize the first current, the period of time being based on the first current.Type: ApplicationFiled: July 2, 2018Publication date: June 6, 2019Applicant: Samsung Electronics Co, LTDInventor: HWANG HO CHOI
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Patent number: 10014907Abstract: An integrated circuit having an eye opening monitor (EOM) is provided. The integrated circuit may include: an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit, wherein the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages, and wherein the comparator divides the target reference voltages from the first and second input voltages respectively by varying a driving capability according to size information data, and compares the first and second input voltages with divided target reference voltages.Type: GrantFiled: December 3, 2015Date of Patent: July 3, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hwang Ho Choi, Duho Kim, JaeHyun Park, Chang-Kyung Seong
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Patent number: 9742596Abstract: A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.Type: GrantFiled: March 24, 2016Date of Patent: August 22, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Prateek Kumar Goyal, Kang-Jik Kim, Jae-Hyun Park, Chang-Kyung Seong, Hwang-Ho Choi
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Patent number: 9537496Abstract: Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.Type: GrantFiled: May 14, 2015Date of Patent: January 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hwang-Ho Choi, Jong-Shin Shin, Seung-Hee Yang, Chang-Kyung Seong
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Publication number: 20160380786Abstract: A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.Type: ApplicationFiled: March 24, 2016Publication date: December 29, 2016Inventors: Prateek Kumar GOYAL, Kang-Jik KIM, Jae-Hyun PARK, Chang-Kyung SEONG, Hwang-Ho CHOI
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Publication number: 20160209462Abstract: An integrated circuit having an eye opening monitor (EOM) is provided. The integrated circuit may include: an internal circuit; and the EOM configured to measure an eye diagram of a predetermined point of the internal circuit, wherein the EOM may include a comparator configured to receive a first and a second parent reference voltages and a first and a second input voltages output from the internal circuit, and to compare the first and second input voltages with target reference voltages corresponding to the first and second parent reference voltages, and wherein the comparator divides the target reference voltages from the first and second input voltages respectively by varying a driving capability according to size information data, and compares the first and second input voltages with divided target reference voltages.Type: ApplicationFiled: December 3, 2015Publication date: July 21, 2016Inventors: Hwang Ho CHOI, Duho KIM, JaeHyun PARK, Chang-Kyung SEONG
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Publication number: 20160105273Abstract: Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.Type: ApplicationFiled: May 14, 2015Publication date: April 14, 2016Inventors: Hwang Ho CHOI, Jongshin SHIN, Seung-Hee YANG, Chang-Kyung SEONG
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Patent number: 9244179Abstract: An integrated circuit in a PET imaging system with a plurality of photo detectors is provided. A plurality of differential transimpedance amplifiers with differential inputs and differential outputs is provided, wherein differential inputs for each differential transimpedance amplifier of the plurality of differential transimpedance amplifiers are electrically connected to a photodetector.Type: GrantFiled: December 4, 2012Date of Patent: January 26, 2016Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Frances W. Y. Lau, Craig Steven Levin, Mark A. Horowitz, Hwang Ho Choi, Jaeha Kim
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Publication number: 20150001404Abstract: An integrated circuit in a PET imaging system with a plurality of photo detectors is provided. A plurality of differential transimpedance amplifiers with differential inputs and differential outputs is provided, wherein differential inputs for each differential transimpedance amplifier of the plurality of differential transimpedance amplifiers are electrically connected to a photodetector.Type: ApplicationFiled: December 4, 2012Publication date: January 1, 2015Inventors: Frances W. Y. Lau, Craig Steven Levin, Mark A. Horowitz, Hwang Ho Choi, Jaeha Kim