Abstract: A semiconductor memory includes a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and a first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein portions of the third line located in the cell region and over the contact plug contact the second line, and part of a remainder of the third line is spaced apart from the second line.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.

Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.

Abstract: A semiconductor memory includes a substrate including a first region in which a plurality of variable resistance elements are arranged, second and third regions on different sides of the first region, a plurality of first lines disposed over the substrate and extending across the first region and the second region, a plurality of second lines disposed over the first lines and extending across the first region and the third region. The variable resistance elements are positioned at intersections of the first lines and the second lines between the first lines and the second lines, a contact plug is disposed in the third region with an upper end coupled to the second line, and a resistive material layer is interposed between the second line and the variable resistance element in the first region but not between the second line and the contact plug in the third region.

Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.

Abstract: A semiconductor memory includes a substrate including a cell region, a first peripheral circuit region, and a second peripheral circuit region; a plurality of first lines disposed over the substrate across the cell region and the first peripheral circuit region; a plurality of second lines disposed over the first lines across the cell region and the second peripheral circuit region; and a first memory cell positioned at each of intersections between the first lines and the second lines, wherein the cell region includes a first cell region and a second cell region, the first cell region being disposed closer to the first and second peripheral circuit regions than the second cell region, and wherein a first portion of the second line that is in the first cell region has a greater resistance than a second portion of the second line that is in the second cell region.

Abstract: An electronic device comprising a semiconductor memory is provided. The semiconductor memory includes a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region; second lines disposed over the first lines and extending in a second direction crossing the first direction; memory cells positioned at intersections between the first lines and the second lines in the cell region; a first insulating layer positioned between the first lines, between the second line, or both, in the first cell region; and a second insulating layer positioned between the first lines and between the second lines in the second cell region. A dielectric constant of the first insulating layer is smaller than that of the second insulating layer.

Abstract: A semiconductor memory includes: a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and the first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug disposed in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein a portion of the third line, located in the cell region contacts the second line, and another portion of the third line located over the contact plug is spaced apart from the second line.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.

Abstract: A semiconductor memory includes a substrate including a cell region, a first peripheral circuit region, and a second peripheral circuit region; a plurality of first lines disposed over the substrate across the cell region and the first peripheral circuit region; a plurality of second lines disposed over the first lines across the cell region and the second peripheral circuit region; and a first memory cell positioned at each of intersections between the first lines and the second lines, wherein the cell region includes a first cell region and a second cell region, the first cell region being disposed closer to the first and second peripheral circuit regions than the second cell region, and wherein a first portion of the second line that is in the first cell region has a greater resistance than a second portion of the second line that is in the second cell region.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.

Abstract: A semiconductor memory includes a substrate including a first region in which a plurality of variable resistance elements are arranged, second and third regions on different sides of the first region, a plurality of first lines disposed over the substrate and extending across the first region and the second region, a plurality of second lines disposed over the first lines and extending across the first region and the third region. The variable resistance elements are positioned at intersections of the first lines and the second lines between the first lines and the second lines, a contact plug is disposed in the third region with an upper end coupled to the second line, and a resistive material layer is interposed between the second line and the variable resistance element in the first region but not between the second line and the contact plug in the third region.

Abstract: A semiconductor memory includes a substrate including a first region in which a plurality of variable resistance elements are arranged, second and third regions on different sides of the first region, a plurality of first lines disposed over the substrate and extending across the first region and the second region, a plurality of second lines disposed over the first lines and extending across the first region and the third region. The variable resistance elements are positioned at intersections of the first lines and the second lines between the first lines and the second lines, a contact plug is disposed in the third region with an upper end coupled to the second line, and a resistive material layer is interposed between the second line and the variable resistance element in the first region but not between the second line and the contact plug in the third region.

Abstract: A semiconductor memory includes: a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and the first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug disposed in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein a portion of the third line, located in the cell region contacts the second line, and another portion of the third line located over the contact plug is spaced apart from the second line.

Abstract: A semiconductor memory includes a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and a first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein portions of the third line located in the cell region and over the contact plug contact the second line, and part of a remainder of the third line is spaced apart from the second line.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.

Abstract: A semiconductor memory includes a substrate including a first region in which a plurality of variable resistance elements are arranged, second and third regions on different sides of the first region, a plurality of first lines disposed over the substrate and extending across the first region and the second region, a plurality of second lines disposed over the first lines and extending across the first region and the third region. The variable resistance elements are positioned at intersections of the first lines and the second lines between the first lines and the second lines, a contact plug is disposed in the third region with an upper end coupled to the second line, and a resistive material layer is interposed between the second line and the variable resistance element in the first region but not between the second line and the contact plug in the third region.

Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.

Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.

Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.