Abstract: Provided is a positive electrode active material including a plurality of crystallites A, wherein the plurality of crystallites A has a crystallite long-axis orientation degree DoA represented by Equation 1 below is 0.5 to 1, and a crystallite c-axis orientation degree represented by a cross product value of a c-axis rotation vector Rc of a crystal lattice of a crystallite obtained by electron backscatter diffraction (EBSD) analysis and a position unit vector P? of the crystallite is 0.5 to 1. A proportion of the plurality of crystallites A is 25% to 80% with respect to a total number of crystallites in a cross-section of a positive electrode active material. Further provided is a positive electrode and a lithium secondary battery including the positive electrode active material.

Abstract: A semiconductor package including: a first substrate; a first semiconductor device on the first substrate; a first mold layer covering the first semiconductor device; a second substrate on the first mold layer; a support solder ball interposed between the first substrate and the second substrate, and electrically disconnected from the first substrate or the second substrate, wherein the support solder ball includes a core and is disposed near a first sidewall of the first semiconductor device; and a substrate connection solder ball disposed between the first sidewall of the first semiconductor device and the support solder ball to electrically connect the first substrate to the second substrate, wherein a top surface of the first semiconductor device has a first height from a top surface of the first substrate, and the core has a second height which is equal to or greater than the first height.

Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.

Abstract: A semiconductor package includes a substrate, a first chip stack on the substrate and including a first semiconductor chip, an underfill pattern on a first side of the first chip stack, and a second chip stack on the first chip stack and including a second semiconductor chip. The second chip stack is stacked so as to be offset to the first chip stack. The first chip stack includes a first adhesive layer under the first semiconductor chip and a first chip protection structure on the first semiconductor chip. The second chip stack includes a second adhesive layer under the second semiconductor chip and a second chip protection structure on the second semiconductor chip. An extension portion of the second adhesive layer is on one side of the first chip protection structure, and the underfill pattern extends from the first side of the first chip stack to the extension portion.

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

Abstract: A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

Abstract: A semiconductor package including: a first substrate; a first semiconductor device on the first substrate; a first mold layer covering the first semiconductor device; a second substrate on the first mold layer; a support solder ball interposed between the first substrate and the second substrate, and electrically disconnected from the first substrate or the second substrate, wherein the support solder ball includes a core and is disposed near a first sidewall of the first semiconductor device; and a substrate connection solder ball disposed between the first sidewall of the first semiconductor device and the support solder ball to electrically connect the first substrate to the second substrate, wherein a top surface of the first semiconductor device has a first height from a top surface of the first substrate, and the core has a second height which is equal to or greater than the first height.

Abstract: A semiconductor package includes; a substrate including a first insulating layer and a first conductive pattern in the first insulating layer, a first semiconductor chip on the substrate, an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate and including a second insulating layer and a second conductive pattern in the second insulating layer, a first element between the first semiconductor chip and the interposer, a connection member between the substrate and the interposer, and a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.

Abstract: A semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between a first surface of the semiconductor chip and the substrate; and a redistribution layer provided on a second surface, opposite to the first surface, of the semiconductor chip. The substrate includes substrate patterns, and the substrate patterns cover a second surface of the substrate. The substrate patterns cover 60% to 100% of a total area of the second surface of the substrate.

Abstract: A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

Abstract: A semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between a first surface of the semiconductor chip and the substrate; and a redistribution layer provided on a second surface, opposite to the first surface, of the semiconductor chip. The substrate includes substrate patterns, and the substrate patterns cover a second surface of the substrate. The substrate patterns cover 60% to 100% of a total area of the second surface of the substrate.

Abstract: Disclosed herein is a method for forming quantum dots, comprising the steps of (a) depositing a metal thin layer onto a substrate, (b) coating a dielectric precursor onto the metal thin layer, and (c) stepwisely heating the resultant substrate; or a method for forming quantum dots, comprising the steps of (a) mixing a dielectric precursor diluted in a solvent and a metal powder and stirring the mixture, (b) coating the mixture onto a substrate, and (c) heating the resultant substrate. The method can easily control the size, density and uniformity of metal oxide quantum dots.

Abstract: Disclosed herein is a method for forming quantum dots, comprising the steps of (a) depositing a metal thin layer onto a substrate, (b) coating a dielectric precursor onto the metal thin layer, and (c) stepwisely heating the resultant substrate; or a method for forming quantum dots, comprising the steps of (a) mixing a dielectric precursor diluted in a solvent and a metal powder and stirring the mixture, (b) coating the mixture onto a substrate, and (c) heating the resultant substrate. The method can easily control the size, density and uniformity of metal oxide quantum dots.