Abstract: Disclosed are a semiconductor package made from the first and second panel-level methods with at least one pre-made conductive unit. The semiconductor package includes one or more semiconductor dies, a molding layer for encapsulating the one or more semiconductor dies; at least one pre-made conductive unit prepared from a molded conductive substrate; a front build-up layer electrically coupled to the semiconductor dies and the at least one pre-made conductive unit; and an external connection layer electrically coupled to the front build-up layer. The semiconductor dies and pre-made conductive unit may be arranged in either a side-by-side configuration or a vertical configuration. The present application further discloses panel-level methods of making the semiconductor package with the at least one pre-made conductive unit. The present application further relates to several methods of preparing the at least one pre-made conductive unit.

Abstract: A die bonding apparatus including: a carrier support unit having at least one support element defining a supporting plane and a carrier holder operable to support the carrier panel on a side of the supporting plane with the carrier panel being parallel to the supporting plane; a wafer feed unit having a wafer holder operable to hold a diced wafer in a manner so as to space the diced wafer apart from the supporting plane defined by the at least one support element of the carrier support unit and orient the diced wafer with an exposed surface of the diced wafer facing the side of the supporting plane to which the carrier panel is supported; and a die transfer module disposed between the carrier support unit and the wafer feed unit, the die transfer module operable to transfer a die from the diced wafer to the carrier panel.

Abstract: A power module having a semiconductor package in which all the interconnections are formed by direct copper (Cu). In this way, the power module is suitable for high power efficiency. In addition, the direct copper (Cu) interconnection also enhances heat dissipation of the semiconductor package and thus makes the power module more reliable for operation, particularly under a high temperature. power module further includes a substrate (either a direct bonded copper (DBC) substrate or a ceramic substrate) on which the semiconductor package is mounted on; a plurality of external connecting structures coupled to the substrate for electrically leading out the power module; and at least one signal lead mounted on the substrate.

Abstract: The present application discloses a solder ball attachment jig for preventing warpage of a reconstructed panel in a panel-level semiconductor process, a solder ball attachment system including the solder ball attachment jig, and a method of preventing warpage in attaching solder balls for a panel-level semiconductor process with the solder ball attachment jig. The solder ball attachment jig includes a platform having at least one ejector, and a plate carrier configured to be coupled to the platform for carrying and fixing the reconstructed panel with a plurality of semiconductor dies and a warpage-preventing device. The plate carrier further includes a base plate and at least one releasing hole extending through the base plate, wherein the at least one ejector is configured to be inserted through the at least one releasing hole for releasing the reconstructed panel from the solder ball attachment jig.

Abstract: A die bonding apparatus having: a carrier support unit having at least one support element defining a supporting plane and a carrier holder operable to support the carrier panel on a side of the supporting plane with the carrier panel being parallel to the supporting plane, a wafer feed unit having a wafer holder operable to hold a diced wafer in a manner so as to space the diced wafer apart from the supporting plane defined by the at least one support element of the carrier support unit and orient the diced wafer with an exposed surface of the diced wafer facing the side of the supporting plane to which the carrier panel is supported, and a die transfer module disposed between the carrier support unit and the wafer feed unit, the die transfer module operable to transfer a die from the diced wafer to the carrier panel.

Abstract: A method is disclosed for forming a circuit layer on diverse semiconductor devices, including semiconductor dies and passive packages, within an electronic module. The method comprises generating a Die Location Check (DLC) file to store true positions of the semiconductor devices on a reconstructed panel, Next, a green circuit file specifying the intended positions for the semiconductor devices on the circuit layer is retrieved. Using the DLC file, these intended positions are then adjusted to match the true positions, resulting in an adapted circuit file. Finally, this adapted file guides the formation of the circuit layer, ensuring it aligns precisely with the semiconductor devices. The present application also discloses a method of generating a DLC file for determining true positions of a plurality of semiconductor devices in a reconstructed panel. The present application further discloses a panel-level semiconductor packaging method for making a plurality of electronic modules.

Abstract: The present application relates to methods for compensating for die shift during compression molding of semiconductor dies. The method includes using a compensated marked carrier which includes a plurality of physical carrier markings derived from original projected markings. These original projected markings are generated through projection of original virtual carrier markings, based on a green file, and are transformed by applying a compensation factor in a computing apparatus. The method includes steps of bonding semiconductor dies onto the compensated marked carrier using the physical carrier markings, and performing compression molding to encapsulate the semiconductor dies into a molded panel. This process adjusts the original gap between adjacent semiconductor dies to a compensated gap, thereby compensating for die shift induced during molding.

Abstract: The present application discloses a semiconductor structure including one or more dies, a protective layer formed on a die active surface, pre-vias formed in the protective layer, and a molding layer encapsulating the die(s) and the protective layer. The die has a die back surface exposed from the molding layer, and the molding layer has a molding thickness larger than a die thickness and a thickness of the protective layer combined for forming a cavity contour. The semiconductor structure also includes a conductive layer formed conformally to the cavity contour for forming a concave contour of the conductive layer. The present application also discloses methods of making the semiconductor structure having a sacrificial layer for solving an issue of die cracking during a thinning process such as backgrinding to a reconstituted panel with the dies embedded within the molding layer.

Abstract: The present disclosure discloses a semiconductor structure having an insulating layer disposed on a wafer active surface of a semiconductor wafer for covering the wafer active surface. The insulating layer may be a protective layer in some embodiments and a cover layer in other embodiments. The insulating layer has via openings to expose contact pads for leading out electrical connections. In particular, the via openings are formed by a multi-step etching process (such as a two-step etching process) without damaging the contact pads. The two-step etching process includes a first laser etching process using normal pulse (P) and normal energy to form partial via openings in the cover layer. The second etching process includes either a laser etching process using low P and low E or a plasma etching process. The second etching process avoids damaging the contact pads.

Abstract: The present disclosure discloses a semiconductor structure having an insulating layer disposed on a wafer active surface of a semiconductor wafer for covering the wafer active surface. The insulating layer may be a protective layer in some embodiments and a cover layer in other embodiments. The insulating layer has via openings to expose contact pads for leading out electrical connections. In particular, the via openings are formed by a multi-step etching process (such as a two-step etching process) without damaging the contact pads. The two-step etching process includes a first laser etching process using normal pulse (P) and normal energy to form partial via openings in the cover layer. The second etching process includes either a laser etching process using low P and low E or a plasma etching process. The second etching process avoids damaging the contact pads.

Abstract: A die bonding apparatus having: a carrier support unit having at least one support element defining a supporting plane and a carrier holder operable to support the carrier panel on a side of the supporting plane with the carrier panel being parallel to the supporting plane, a wafer feed unit having a wafer holder operable to hold a diced wafer in a manner so as to space the diced wafer apart from the supporting plane defined by the at least one support element of the carrier support unit and orient the diced wafer with an exposed surface of the diced wafer facing the side of the supporting plane to which the carrier panel is supported, and a die transfer module disposed between the carrier support unit and the wafer feed unit, the die transfer module operable to transfer a die from the diced wafer to the carrier panel.

Abstract: The present disclosure provides a chip package for power modules including at least one semiconductor die; a driver circuit for controlling the at least one semiconductor die; a protective layer formed on a die active surface of the at least one die and a driver active surface of the driver circuit; a metal unit having at least one metal feature; and a molding layer for encapsulating the at least one semiconductor die, the driver circuit, the protective layer and metal unit. The chip package is connected with an external circuit via the at least one metal feature. The present disclosure also provides a method of making the chip packages for power modules.

Abstract: A semiconductor structure for manufacturing a semiconductor package device is provided. The semiconductor structure includes a carrier and a dielectric layer. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. The dielectric layer is formed on the first surface of the carrier. The carrier supports the dielectric layer.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: A semiconductor structure for manufacturing a semiconductor package device is provided. The semiconductor structure includes a carrier and a dielectric layer. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. The dielectric layer is formed on the first surface of the carrier. The carrier supports the dielectric layer.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.