Patents by Inventor Hwee Seng Chew

Hwee Seng Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446457
    Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 15, 2019
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Shoa Siong Lim, Hwee Seng Chew
  • Publication number: 20190035643
    Abstract: A semiconductor structure for manufacturing a semiconductor package device is provided. The semiconductor structure includes a carrier and a dielectric layer. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. The dielectric layer is formed on the first surface of the carrier. The carrier supports the dielectric layer.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 31, 2019
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Jimmy Hwee-Seng CHEW, Kian-Hock LIM, Oviso Dominador Fortaleza, JR., Shoa-Siong LIM
  • Publication number: 20180323121
    Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 8, 2018
    Inventors: Shoa Siong LIM, Hwee Seng CHEW
  • Patent number: 10109503
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 23, 2018
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Jimmy Hwee-Seng Chew, Oviso Dominador Jr Fortaleza, Kian-Hock Lim, Shoa-Siong Lim
  • Patent number: 10049950
    Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: August 14, 2018
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Shoa Siong Lim, Hwee Seng Chew
  • Patent number: 9120169
    Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: September 1, 2015
    Assignee: ORION SYSTEMS INTEGRATION PTE LTD
    Inventors: Hwee Seng Chew, Chee Kian Ong, Kian Hock Lim, Amlan Sen, Shoa Siong Lim
  • Publication number: 20150155214
    Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.
    Type: Application
    Filed: March 26, 2013
    Publication date: June 4, 2015
    Inventors: Shoa Siong Lim, Hwee Seng Chew
  • Publication number: 20130020710
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 24, 2013
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Jimmy Hwee-Seng Chew, Oviso Dominador Jr. Fortaleza, Kian-Hock Lim, Shoa-Siong Lim
  • Publication number: 20120153465
    Abstract: The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive bump. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive bump, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.
    Type: Application
    Filed: September 1, 2009
    Publication date: June 21, 2012
    Inventors: Jimmy Hwee-Seng Chew, Kian Chee Ong, Kwang Kee Lau
  • Publication number: 20110287560
    Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.
    Type: Application
    Filed: November 9, 2009
    Publication date: November 24, 2011
    Applicant: ORION SYSTEMS INTEGRATION PTE LTD
    Inventors: Hwee Seng Chew, Chee Kian Ong, Kian Hock Lim, Amlan Sen, Shoa Siong Lim
  • Patent number: 7692440
    Abstract: A water jet handler (200) has a loading location (205), a cutting location (210), and an unloading location (215); and two movable mounts (240 and a 245). As a first movable mount (240) receives a molded substrate at the loading location (205), and transports it to the cutting location (210), a second movable mount (245) transports singulated semiconductor packages of a previously singulated molded substrate from the cutting location (210) to the unloading location (215). As the molded substrate on the first movable mount (240) is cut in the X direction (232) by a water jet, the singulated semiconductor packages are unloaded. The molded substrate is then transferred to the second movable mount (245) on which it is cut in the Y direction (272) to produce singulated semiconductor packages, as the first movable mount (240) returns to the loading location (205), when another molded substrate is loaded.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 6, 2010
    Assignee: Advanced Systems Automation Limited
    Inventors: Jimmy Hwee Seng Chew, Kok Yeow Lim, Fulin Liu
  • Publication number: 20080248610
    Abstract: The present invention provides a thermal bonding process for chip packaging. In accordance with an aspect of the invention, there is provided an approach to solve the problems caused by the different CTEs between the die and the substrate. It discloses an improved thermal bonding process for forming pillar-shaped interconnection, which controls the thermal expansion of the semiconductor die and the substrate by applying differential heating temperature to the two, thereby minimizing the misalignment between the die and the substrate, overcoming the stresses imposed on the interconnection and allowing more reliable and accurate packaging.
    Type: Application
    Filed: April 3, 2007
    Publication date: October 9, 2008
    Applicant: Advanpack Solutions Pte Ltd
    Inventors: Hwee Seng Chew, Chee Kian Ong, Balasubramanian Sivagnanam
  • Publication number: 20070196979
    Abstract: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 23, 2007
    Applicant: Advanpack Solutions Pte Ltd
    Inventors: Teck Tan, Hwee Seng Chew, Kok Yeow Lim, Abd. Razak Chichik, Kee Lau, Chuan Wong
  • Publication number: 20060103016
    Abstract: High performance integrated circuits generally have high heat generating capabilities. During powering up of these integrated circuits under typical operating conditions, heat generation is unavoidably accelerated. When the accumulated heat is not adequately dissipated, the high temperature of the integrated circuits will lead to overheating which in turn, causes irreversible damage to the integrated circuits. Conventional thermal management methods using bumps of a ball grid array (BGA) as heat paths to a heat sink has low thermal transmissibility due to the substantially spherical shape thereof. Metallic columns formed by vias in substrates have dimensional restrictions that also limit thermal transmissibility thereof. Coupling of semiconductor device directly to a heat sink formed in a substrate will also require undesirable structural modifications to the substrate, for example a concavity formed therein, for accommodating the integrated circuit therewithin.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Applicant: Advanpack Solutions Pte Ltd
    Inventors: Teck Tan, Hwee Seng Chew
  • Patent number: 6550666
    Abstract: A predetermined amount of solder (315) is deposited on the free ends of copper posts (310) extending from die pads of a semiconductor die (305). The solder (315) is coated with flux (320) and the semiconductor die (305) is placed on a leadframe (100) with the solder deposits (315) abutting interconnect locations (335) on inner lead portions (101). When reflowed, the solder deposits (315) melt and with the assistance of the flux (320) forms solder interconnects between the free ends of the copper posts (310) and the interconnect locations (335). Due to the predetermined amount of solder (315) deposited on the free ends of the copper posts (310), the molten solder (315) tends not to flow away from the interconnect location (335). Thus, advantageously allowing a substantial portion of the solder deposit (315) to remain at the interconnect locations (335) to form solder interconnects.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: April 22, 2003
    Assignee: Advanpack Solutions Pte LTD
    Inventors: Jimmy Hwee Seng Chew, Kim Hwee Tan
  • Publication number: 20030038162
    Abstract: A predetermined amount of solder (315) is deposited on the free ends of copper posts (310) extending from die pads of a semiconductor die (305). The solder (315) is coated with flux (320) and the semiconductor die (305) is placed on a leadframe (100) with the solder deposits (315) abutting interconnect locations (335) on inner lead portions (101). When reflowed, the solder deposits (315) melt and with the assistance of the flux (320) forms solder interconnects between the free ends of the copper posts (310) and the interconnect locations (335). Due to the predetermined amount of solder (315) deposited on the free ends of the copper posts (310), the molten solder (315) tends not to flow away from the interconnect location (335). Thus, advantageously allowing a substantial portion of the solder deposit (315) to remain at the interconnect locations (335) to form solder interconnects.
    Type: Application
    Filed: August 21, 2001
    Publication date: February 27, 2003
    Inventors: Jimmy Hwee Seng Chew, Kim Hwee Tan