Abstract: A method for manufacturing an interconnect structure includes: forming a via opening in a dielectric layer, an inner wall surface of the dielectric layer defining the via opening and having an annular top view shape which has a first dimension in a first plane and a second dimension in a second plane, the first plane intersecting the inner wall surface to form two first lines, the second plane intersecting the inner wall surface to form two second lines; subjecting the inner wall surface to an etching rate modification treatment, so that the inner wall surface has etching rates gradually increasing from each of the first lines to each of the second lines; subjecting the inner wall surface to an etching process, so that the second dimension is elongated to be greater than the first dimension; and forming a contact via in the via opening.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.

Abstract: A semiconductor device includes a substrate, an interconnect layer disposed over the substrate and including a metal line, and a dielectric layer disposed on the interconnect layer and including a via contact. The via contact is electrically connected to the metal line and has a first dimension in a first direction greater than a second dimension in a second direction. The first direction and the second direction are perpendicular to each other, and are both perpendicular to a longitudinal direction of the via contact.

Abstract: A method for manufacturing a semiconductor device includes: forming metal lines on a conductive interconnect structure disposed on a substrate; forming functionalized polymers, each of which includes a carbon-based polymer chain and a functional group that is bonded to a lateral surface of a corresponding one of the metal lines and that is represented by formula (A): wherein R1, R2, R3 are defined herein; removing the carbon-based polymer chain of an upper portion of the functionalized polymers to leave the carbon-based polymer chain of remainder of the functionalized polymers and to form recesses; forming a dielectric layer to fill the recesses; and removing the carbon-based polymer chain of the remainder of the functionalized polymers to form air gaps among the metal lines.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes: a conductive layer, disposed over a substrate; a first conductive structure, disposed over the conductive layer; an isolating member, disposed over the conductive layer and separated from the first conductive structure, wherein the first conductive structure and the isolating member are surrounded by a first dielectric layer; a first conductive member, disposed on isolating member; and a second conductive member, disposed on the first conductive structure and the first dielectric layer. The first conductive member and the first conductive structure extend along a first direction. The second conductive member extends along a second direction perpendicular to the first direction.

Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.

Abstract: A method includes patterning a metal layer on a substrate to form two metal lines spaced apart from each other by a recess, forming a directed self-assembly (DSA) segment in the recess, wherein the DSA segment includes block co-polymer (BCP), performing a phase separation process on the DSA segment to cause two components of the BCP to separate from each other to form a first polymer block and a second polymer block that are aligned next to each other in the recess, and removing the second polymer block to form an air gap that is bordered by the first polymer block and that is located between the metal lines.

Abstract: A conductive interconnection structure includes a conductive feature part, a dielectric structure, a trench filling portion, a via portion and a metal layer. The dielectric structure is formed over the conductive feature part. The dielectric structure includes a first dielectric layer and a second dielectric layer stacked on each other. The second dielectric layer covers the first dielectric layer. The trench filling portion is embedded in the dielectric structure, and the trench filling portion and the second dielectric layer have different etching selectivities. The via portion is located in the first dielectric layer at the bottom surface of the trench filling portion. The metal layer penetrates the dielectric structure, the trench filling portion and the via portion, and the bottom surface of the metal layer is electrically connected to the conductive feature part.

Abstract: A semiconductor device includes a substrate, a conductive interconnect structure disposed on the substrate, a plurality of air gap structures disposed on the conductive interconnect structure and spaced apart from each other, and a plurality of conductive interconnects disposed on the conductive interconnect structure and alternating with the plurality of the air gap structures. Each of the plurality of the air gap structures includes a dielectric portion and an air gap. The air gap of each of the plurality of the air gap structures is confined by the dielectric portion of the each of the plurality of the air gap structures and two corresponding ones of the plurality of the conductive interconnects.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a conductive structure over the substrate. The semiconductor device structure also includes a catalyst structure over the conductive structure and a carbon-containing conductive via on the catalyst structure. A top of the catalyst structure is closer to the substrate than a top of the carbon-containing via, and a bottom of the carbon-containing conductive via is closer to the substrate than the top of the catalyst structure.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a conductive line over the substrate. The semiconductor device structure also includes a catalyst structure over the conductive line and a carbon-containing conductive via directly on the catalyst structure. The semiconductor device structure further includes a dielectric layer surrounding the carbon-containing conductive via.

Abstract: A semiconductor device includes a MEOL structure and a BEOL structure. The BEOL structure is formed over the MEOL structure and includes a first dielectric layer, a spacer and a conductive portion. The first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. The spacer is formed the lateral surface and covers an opening of the recess. The conductive portion is formed adjacent to the spacer.

Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.

Abstract: A method for forming a semiconductor structure includes following operations. A first metallization feature is formed, and a first cap layer is formed over the first metallization feature. A first insulating layer is formed over the first cap layer and the first metallization feature. A first dielectric structure is formed over the first insulating layer. A portion of the first dielectric structure and a portion of the first insulating layer are removed to expose the first cap layer. A second cap layer is formed over the first cap layer and the first metallization feature. A second insulating layer and a patterned second dielectric structure are formed over the substrate. The patterned second dielectric structure includes a trench and a via opening coupled to a bottom of the trench. A second metallization feature is formed in the trench, and a via structure is formed in the via opening.

Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.

Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.