Patents by Inventor Hwei-Jay CHU

Hwei-Jay CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133800
    Abstract: A semiconductor device includes a MEOL structure and a BEOL structure. The BEOL structure is formed over the MEOL structure and includes a first dielectric layer, a spacer and a conductive portion. The first dielectric layer has a lateral surface and a recess, wherein the recess is recessed with respect to the lateral surface. The spacer is formed the lateral surface and covers an opening of the recess. The conductive portion is formed adjacent to the spacer.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Chih-Wei LU, Cheng-Hao CHEN
  • Publication number: 20250125189
    Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Hwei-Jay CHU, Yu-Teng DAI, Hsin-Chieh YAO, Yung-Hsu WU, Li-Ling SU, Chia-Wei SU, Hsin-Ping CHEN
  • Publication number: 20250118656
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: HWEI-JAY CHU, HSI-WEN TIEN, WEI-HAO LIAO, YU-TENG DAI, HSIN-CHIEH YAO, CHENG-HAO CHEN, CHIH WEI LU
  • Publication number: 20250112087
    Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
  • Publication number: 20250087535
    Abstract: A method for forming a semiconductor structure includes following operations. A first metallization feature is formed, and a first cap layer is formed over the first metallization feature. A first insulating layer is formed over the first cap layer and the first metallization feature. A first dielectric structure is formed over the first insulating layer. A portion of the first dielectric structure and a portion of the first insulating layer are removed to expose the first cap layer. A second cap layer is formed over the first cap layer and the first metallization feature. A second insulating layer and a patterned second dielectric structure are formed over the substrate. The patterned second dielectric structure includes a trench and a via opening coupled to a bottom of the trench. A second metallization feature is formed in the trench, and a via structure is formed in the via opening.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Patent number: 12165920
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee
  • Publication number: 20240379437
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Publication number: 20240266212
    Abstract: A method for manufacturing a semiconductor device includes: forming metal lines on a conductive interconnect structure disposed on a substrate; forming functionalized polymers, each of which includes a carbon-based polymer chain and a functional group that is bonded to a lateral surface of a corresponding one of the metal lines and that is represented by formula (A): wherein R1, R2, R3 are defined herein; removing the carbon-based polymer chain of an upper portion of the functionalized polymers to leave the carbon-based polymer chain of remainder of the functionalized polymers and to form recesses; forming a dielectric layer to fill the recesses; and removing the carbon-based polymer chain of the remainder of the functionalized polymers to form air gaps among the metal lines.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Yu-Teng DAI, Chih-Wei LU, Hsin-Chieh YAO, Hwei-Jay CHU
  • Publication number: 20240021472
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Application
    Filed: May 28, 2023
    Publication date: January 18, 2024
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
  • Publication number: 20230387022
    Abstract: A semiconductor device includes a substrate, an interconnect layer disposed over the substrate and including a metal line, and a dielectric layer disposed on the interconnect layer and including a via contact. The via contact is electrically connected to the metal line and has a first dimension in a first direction greater than a second dimension in a second direction. The first direction and the second direction are perpendicular to each other, and are both perpendicular to a longitudinal direction of the via contact.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsi-Wen TIEN, Hwei-Jay CHU, Chia-Tien WU, Yung-Hsu WU, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Hsin-Ping CHEN, Chih-Wei LU
  • Patent number: 11830910
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han Wu, Hwei-Jay Chu, An-Dih Yu, Tzu-Hui Wei, Cheng-Hsiung Tsai, Chung-Ju Lee, Shin-Yi Yang, Ming-Han Lee
  • Publication number: 20230378255
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han WU, Hwei-Jay CHU, An-Dih YU, Tzu-Hui WEI, Cheng-Hsiung TSAI, Chung-Ju LEE, Shin-Yi YANG, Ming-Han LEE
  • Publication number: 20230230881
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a conductive line over the substrate. The semiconductor device structure also includes a catalyst structure over the conductive line and a carbon-containing conductive via directly on the catalyst structure. The semiconductor device structure further includes a dielectric layer surrounding the carbon-containing conductive via.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Yu-Teng DAI, Chih-Wei LU, Hsin-Chieh YAO, Hwei-Jay CHU
  • Patent number: 11676862
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee
  • Publication number: 20230062416
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han WU, Hwei-Jay CHU, An-Dih YU, Tzu-Hui WEI, Cheng-Hsiung TSAI, Chung-Ju LEE, Shin-Yi YANG, Ming-Han LEE
  • Publication number: 20230062825
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Publication number: 20230039661
    Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.
    Type: Application
    Filed: March 15, 2022
    Publication date: February 9, 2023
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Wei-Hao LIAO, Yu-Teng DAI, Hsi-Wen TIEN, Chih Wei LU
  • Publication number: 20220277995
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
  • Patent number: 11393718
    Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chih-Wei Lu, Chung-Ju Lee
  • Publication number: 20210242078
    Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.
    Type: Application
    Filed: July 30, 2020
    Publication date: August 5, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Cheng-Hsiung TSAI, Chih-Wei LU, Chung-Ju LEE