Patents by Inventor Hwi-jong YOO

Hwi-jong YOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210022249
    Abstract: A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-guk SEO, Sun-ki YUN, Su-jin KIM, Hwi-jong YOO, Young-rok OH
  • Patent number: 10840221
    Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ilsoo Kim, Heeyoub Kang, Young-Rok Oh, Kitaek Lee, Hwi-Jong Yoo
  • Patent number: 10820419
    Abstract: A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-guk Seo, Sun-ki Yun, Su-jin Kim, Hwi-jong Yoo, Young-rok Oh
  • Publication number: 20200176423
    Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Inventors: ILSOO KIM, HEEYOUB KANG, YOUNG-ROK OH, KITAEK LEE, HWI-JONG YOO
  • Patent number: 10593648
    Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ilsoo Kim, Heeyoub Kang, Young-Rok Oh, Kitaek Lee, Hwi-Jong Yoo
  • Patent number: 10529692
    Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ilsoo Kim, Heeyoub Kang, Young-Rok Oh, Kitaek Lee, Hwi-Jong Yoo
  • Publication number: 20190373730
    Abstract: A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.
    Type: Application
    Filed: December 3, 2018
    Publication date: December 5, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-guk SEO, Sun-ki YUN, Su-jin KIM, Hwi-jong YOO, Young-rok OH
  • Patent number: 10212808
    Abstract: Disclosed is a printed circuit hoard. The printed circuit board includes a plurality of insulation layers and a plurality of pattern layers alternately stacked. The printed circuit board includes a plurality of device areas on which semiconductor packages are mounted and a peripheral area adjacent the device areas. An electrostatic discharge pattern is in a respective pattern layer among the plurality of pattern layers and is disposed at a boundary region between a respective device area of the plurality of device areas and the peripheral area.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Iksung Park, Heeyoub Kang, Young-Min Kim, Eunji You, Hwi-jong Yoo
  • Publication number: 20180323175
    Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.
    Type: Application
    Filed: July 2, 2018
    Publication date: November 8, 2018
    Inventors: ILSOO KIM, HEEYOUB KANG, YOUNG-ROK OH, KITAEK LEE, HWI-JONG YOO
  • Patent number: 10068828
    Abstract: A semiconductor storage device includes a circuit substrate. The circuit substrate includes a main body and a connection tab connected to a side of the main body. The a main body includes a first chip mounting region and a second chip mounting region. A first semiconductor chip of a first type is mounted on the first chip mounting region. A second semiconductor chip of a second type is mounted on the second chip mounting region. The first type of the first semiconductor chip is different from the second type of the second semiconductor chip. The circuit substrate further includes a first thermal via in the connection tab and comprising a conductive material.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Young Choi, Young-Rok Oh, Hwi-Jong Yoo, Il-Soo Kim, Joo-Young Kim, Ki-Taek Lee, Eun-Ji Yu
  • Publication number: 20180158752
    Abstract: A semiconductor storage device includes a circuit substrate. The circuit substrate includes a main body and a connection tab connected to a side of the main body. The a main body includes a first chip mounting region and a second chip mounting region. A first semiconductor chip of a first type is mounted on the first chip mounting region. A second semiconductor chip of a second type is mounted on the second chip mounting region. The first type of the first semiconductor chip is different from the second type of the second semiconductor chip. The circuit substrate further includes a first thermal via in the connection tab and comprising a conductive material.
    Type: Application
    Filed: April 4, 2017
    Publication date: June 7, 2018
    Inventors: MIN-YOUNG CHOI, YOUNG-ROK OH, HWI-JONG YOO, IL-SOO KIM, JOO-YOUNG KIM, KI-TAEK LEE, EUN-JI YU
  • Publication number: 20180138154
    Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 17, 2018
    Inventors: ILSOO KIM, HEEYOUB KANG, YOUNG-ROK OH, KITAEK LEE, HWI-JONG YOO
  • Patent number: 9888565
    Abstract: A memory module includes a module board extending in one direction, a plurality of electronic elements mounted on the module board, and at least one stress detection pattern in a position between the electronic elements or adjacent to one or more of the electronic elements on the module board and including a plurality of strips configured to indicate a stress level generated in the position by an external force applied to the module board.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: February 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Kyu Bang, Yusuf Cinar, Hwi-Jong Yoo
  • Publication number: 20170094781
    Abstract: A memory module includes a module board extending in one direction, a plurality of electronic elements mounted on the module board, and at least one stress detection pattern in a position between the electronic elements or adjacent to one or more of the electronic elements on the module board and including a plurality of strips configured to indicate a stress level generated in the position by an external force applied to the module board.
    Type: Application
    Filed: June 8, 2016
    Publication date: March 30, 2017
    Inventors: Kwang-Kyu Bang, Yusuf Cinar, Hwi-Jong Yoo
  • Publication number: 20170048970
    Abstract: Disclosed is a printed circuit hoard. The printed circuit board includes a plurality of insulation layers and a plurality of pattern layers alternately stacked, The printed circuit board includes a plurality of device areas on which semiconductor packages are mounted and a peripheral area adjacent the device areas. An electrostatic discharge pattern is in a respective pattern layer among the plurality of pattern layers and is disposed at a boundary region between a respective device area of the plurality of device areas and the peripheral area.
    Type: Application
    Filed: April 7, 2016
    Publication date: February 16, 2017
    Inventors: Iksung Park, Heeyoub KANG, Young-Min KIM, Eunji YOU, Hwi-jong YOO