Abstract: Provided are a touch processor for performing active protection, a touch display driver integrated circuit (DDI) chip including the touch processor, and a method of operating the touch processor. The touch processor for driving a touch panel including a sensing cell includes a driving circuit configured to provide a driving signal to the touch panel, and a capacitance controller. The capacitance controller is configured to generate a switch control signal for controlling a switch connected to a sensing unit included in the sensing cell, and a compensation signal having a different waveform than the driving signal, so as to reduce a value of an ambient capacitance component of the sensing cell.

Abstract: A touch sensing apparatus includes a plurality of touch sensors provided in a touch panel and a switching unit for transmitting sensing signals per column or row of the touch sensors through a single line to a touch controller.

Abstract: A touch sensing apparatus includes a plurality of touch sensors provided in a touch panel and a switching unit for transmitting sensing signals per column or row of the touch sensors through a single line to a touch controller.

Abstract: Provided are a touch processor for performing active protection, a touch display driver integrated circuit (DDI) chip including the touch processor, and a method of operating the touch processor. The touch processor for driving a touch panel including a sensing cell includes a driving circuit configured to provide a driving signal to the touch panel, and a capacitance controller. The capacitance controller is configured to generate a switch control signal for controlling a switch connected to a sensing unit included in the sensing cell, and a compensation signal having a different waveform than the driving signal, so as to reduce a value of an ambient capacitance component of the sensing cell.

Abstract: In one embodiment, the touch controller receives touch signals transmitted by a touch panel so as to generate the touch data and perform segmentation based on a peak node of the touch data by assigning labels to neighboring nodes. The method includes determining whether nodes of the touch data are in a touch state by using an energy change of the touch data; selecting a peak node of the touch data; determining a state of the touch data by tracking the peak node; and performing segmentation based on the peak node.

Abstract: A low-voltage data retention circuit and method are provided. The circuit includes a reference voltage generating circuit generating a stable reference voltage, a voltage detecting circuit detecting a voltage of a power supply, a comparing circuit for comparing the detected voltage and the reference voltage, wherein when the detected voltage of the power supply is lower than the reference voltage, the comparing circuit generating a turn-off signal to turn off power consumption modules of an IC chip.

Abstract: An integrated circuit supporting a first interface and a second interface and an integrated circuit card having the same includes the first interface capable of communicating with a first host, the second interface communicating with a second host, and a control block. The control block activates the second interface when a voltage level of a contact that the second host can be connected is in a first state at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host, and deactivates the second interface when the voltage level of the contact is in a second state. The integrated circuit card has the integrated circuit built in.

Abstract: A semiconductor memory device controlling an output voltage level of a high voltage generator in response to a variation of temperature has a high voltage generator that provides a high voltage higher than a power source voltage through an output terminal, generates a temperature detection signal obtained by sensing a variation of a diode current based on a temperature variation, and adjusts a voltage level of the output terminal in response to the temperature detection signal. The device is able to automatically control an output voltage or current of the high voltage generator.

Abstract: A semiconductor memory device controlling an output voltage level of a high voltage generator according to a variation of temperature has a high voltage generator that provides a high voltage higher than a power source voltage through an output terminal, generates a temperature detection signal obtained by sensing a variation of a diode current according to a temperature variation, and adjusts a voltage level of the output terminal in response to the temperature detection signal. The device is able to automatically control an output voltage or current of the high voltage generator. Accordingly, it is possible to control fluctuation of output voltage level or current level due to a voltage variation, thereby lessening degradation of program or erasure characteristics of memory cells that is caused from the fluctuation of the output voltage or current.

Abstract: An integrated circuit supporting a first interface and a second interface and an integrated circuit card having the same includes the first interface capable of communicating with a first host, the second interface communicating with a second host, and a control block. The control block activates the second interface when a voltage level of a contact that the second host can be connected is in a first state at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host, and deactivates the second interface when the voltage level of the contact is in a second state. The integrated circuit card has the integrated circuit built in.

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract: Methods and apparatuses for changing capacitance are provided. The apparatus may adjust a current supplied to a load capacitor according to the frequency of an input clock signal. When operating at a lower frequency, a capacitance may be increased such that noise immunity may be increased. When operating at a higher frequency, a capacitance may be decreased such that current consumption may be reduced.

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks.

Abstract: A flash memory device provides for a stable source line regardless of bit line coupling during a read operation and regardless of loading effect during a manufacturing process.

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks.

Abstract: A flash memory device provides for a stable source line regardless of bit line coupling during a read operation and regardless of loading effect during a manufacturing process.

Abstract: A boosting unit comprises a plurality of boosting circuits. Each boosting circuit includes an input driving circuit, a switching circuit, a capacitor circuit, and a precharge circuit. The input driving circuit drives a corresponding external boosting signal. The switching circuit transfers either a power supply voltage, a ground voltage, or a boosting signal from one of the other boosting circuits to the capacitor circuit under the control of the corresponding external boosting signal. The capacitor circuit boosts up a boosting node, which has been precharged to a power supply voltage level by the precharge circuit, to predetermined voltage level higher than an input voltage level. The boosting circuits are connected together in series and simultaneously carry out a boosting operation. The boosting unit therefore provides a desired boosted voltage level at high speed.

Abstract: The invention provides decoder circuits for selecting a word line in a semiconductor memory device which comprises a plurality of memory cell sectors including a plurality of word lines and bit lines and a plurality of memory cells which each is electrically erasable and programmable. The decoder circuits comprise a pull-up and pull-down transistors connected to global word lines which are connected to the word lines via connecting means, the decoder circuits turning on pull-down transistors before a high voltage according to an operation mode is supplied to one selected from the global word lines and pre-charging the gates of the pull-up transistors to the high voltage. The invention enables the decoder circuits to supply the word line drive voltage to the global word lines connected to memory cells by using the self-boosting method to thereby reduce the boosting load.

Abstract: A nonvolatile semiconductor memory device is provided, which supports an erase verify operation mode to determine whether an erased memory cell is lower than a maximal threshold voltage (e.g., 3V), and a test verify operation mode to determine whether the erased memory cell has a progressive fail characteristic. Once the memory device enters the test verify operation mode, a wordline voltage to be applied to a memory cell and a reference wordline voltage to be applied to a reference cell are generated. The wordline and reference wordline voltages generated in the test verify operation mode are set to be higher than those generated in the erase verify operation mode. This makes it possible to compare current flowing through the memory cell and reference cell at more than one level and to check a memory cell for a progressive (or potential) failing characteristic.