Patents by Inventor Hwong-Kwo Lin
Hwong-Kwo Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10672461Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.Type: GrantFiled: January 22, 2014Date of Patent: June 2, 2020Assignee: Nvidia CorporationInventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
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Patent number: 10181842Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.Type: GrantFiled: November 18, 2015Date of Patent: January 15, 2019Assignee: NVIDIA CORPORATIONInventors: Ge Yang, Xi Zhang, Jiani Yu, Lingfei Deng, Hwong-Kwo Lin
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Patent number: 9842631Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.Type: GrantFiled: December 14, 2012Date of Patent: December 12, 2017Assignee: NVIDIA CORPORATIONInventors: Ge Yang, Hwong-Kwo Lin, Xi Zhang, Jiani Yu, Haiyan Gong
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Publication number: 20170141768Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.Type: ApplicationFiled: November 18, 2015Publication date: May 18, 2017Inventors: Ge YANG, Xi ZHANG, Jiani YU, Lingfei DENG, Hwong-Kwo LIN
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Patent number: 9542992Abstract: A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.Type: GrantFiled: April 18, 2013Date of Patent: January 10, 2017Assignee: NVIDIA CorporationInventors: Hwong-Kwo Lin, Ge Yang, Fei Song, Xi Zhang, Haiyan Gong
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Patent number: 9525401Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.Type: GrantFiled: March 11, 2015Date of Patent: December 20, 2016Assignee: NVIDIA CORPORATIONInventors: Xi Zhang, Hwong-Kwo Lin, Ge Yang, Lingfei Deng
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Publication number: 20160336054Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Stephen FELIX, Hwong-Kwo LIN, Spencer GOLD, Jing GUO, Andreas GOTTERBA, Jason GOLBUS, Karthik NATARAJAN, Jun YANG, Zhenye JIANG, Ge YANG, Lei WANG, Yong LI, Hua CHEN, Haiyan GONG, Beibei REN, Eric VOELKEL
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Patent number: 9496047Abstract: In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.Type: GrantFiled: August 27, 2013Date of Patent: November 15, 2016Assignee: NVIDIA CORPORATIONInventors: Jun Yang, Hwong-Kwo Lin, Hua Chen, Yong Li, Ju Shen
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Patent number: 9484115Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.Type: GrantFiled: May 13, 2015Date of Patent: November 1, 2016Assignee: NVIDIA CorporationInventors: Stephen Felix, Hwong-Kwo Lin, Spencer Gold, Jing Guo, Andreas Gotterba, Jason Golbus, Karthik Natarajan, Jun Yang, Zhenye Jiang, Ge Yang, Lei Wang, Yong Li, Hua Chen, Haiyan Gong, Beibei Ren, Eric Voelkel
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Publication number: 20160269002Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.Type: ApplicationFiled: March 11, 2015Publication date: September 15, 2016Inventors: Xi Zhang, Hwong-Kwo Lin, Ge Yang, Lingfei Deng
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Patent number: 9390788Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.Type: GrantFiled: July 27, 2015Date of Patent: July 12, 2016Assignee: Nvidia CorporationInventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Patent number: 9355710Abstract: A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.Type: GrantFiled: January 23, 2014Date of Patent: May 31, 2016Assignee: NVIDIA CORPORATIONInventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
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Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failure
Patent number: 9219480Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).Type: GrantFiled: January 31, 2014Date of Patent: December 22, 2015Assignee: Nvidia CorporationInventors: Hwong-Kwo Lin, Ge Yang, Xi Zhang, Ying Huang -
Publication number: 20150332757Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Inventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Patent number: 9183922Abstract: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.Type: GrantFiled: May 24, 2013Date of Patent: November 10, 2015Assignee: NVIDIA CorporationInventors: Jun Yang, Hwong-Kwo Lin, Ju Shen, Yong Li, Hua Chen
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Patent number: 9123438Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.Type: GrantFiled: October 15, 2013Date of Patent: September 1, 2015Assignee: Nvidia CorporationInventors: Hwong-Kwo Lin, Lei Wang, Spencer Gold, Zhenye Jiang
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Publication number: 20150235681Abstract: A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included.Type: ApplicationFiled: May 16, 2014Publication date: August 20, 2015Applicant: Nvidia CorporationInventors: Gang Chen, Jing Guo, Yiqi Wang, Hwong-Kwo Lin
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Patent number: 9110141Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.Type: GrantFiled: November 2, 2012Date of Patent: August 18, 2015Assignee: NVIDIA CorporationInventors: Hwong-Kwo Lin, Ge Yang, Xi Zhang, Jiani Yu, Ting-Hsiang Chu
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LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE
Publication number: 20150222266Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Applicant: Nvidia CorporationInventors: Hwong-Kwo Lin, Ge Yang, Xi Zhang, Ying Huang -
Publication number: 20150206576Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Applicant: Nvidia CorporationInventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang