Patents by Inventor Hyae-Ryoung Lee
Hyae-Ryoung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7534677Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.Type: GrantFiled: January 14, 2005Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyae-ryoung Lee, Su-gon Bae
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Publication number: 20050170575Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.Type: ApplicationFiled: January 14, 2005Publication date: August 4, 2005Inventors: Hyae-ryoung Lee, Su-gon Bae
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Patent number: 6597032Abstract: Metal-insulator-metal capacitors include a first capacitor electrode comprising a first metal extending on a substrate and a first electrically insulating layer comprising a first material extending on the first capacitor electrode. The first electrically insulating layer has a first opening therein that exposes a first portion of the first capacitor electrode. An electrically insulating etch-stop layer that comprises a second material different from the first material, extends on the first electrically insulating layer and has a second opening therein. A capacitor dielectric layer extends on the exposed first portion of the first capacitor electrode and on sidewalls of the first electrically insulating layer and the etch-stop layer. A second capacitor electrode that comprises a second metal extends on the capacitor dielectric layer and opposite the first capacitor electrode. The first and second metals may both comprise copper, gold or aluminum.Type: GrantFiled: February 1, 2000Date of Patent: July 22, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Hyae-Ryoung Lee
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Patent number: 6569746Abstract: Disclosed is a capacitor of semiconductor integrated circuit and a method for fabricating the same by which characteristic of a capacitor and bit resolution can be improved to thereby obtain an improved analog device of high accuracy. The capacitor of semiconductor integrated circuit includes a conductive lower electrode formed on a predetermined portion of an insulating substrate, an insulating layer formed on the insulating substrate including the conductive lower electrode and provided with a via hole so that the surface of the lower electrode is exposed in its predetermined portion, a dielectric layer formed on the insulating layer and in the via hole, and an conductive upper electrode formed on the predetermined portion of the dielectric layer including the via hole to have a piled structure such as “conductive plug/conductive layer pattern”.Type: GrantFiled: December 8, 2000Date of Patent: May 27, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Hyae-Ryoung Lee, Sun-Il Yu, Dong-Woo Kim
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Patent number: 6552438Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.Type: GrantFiled: December 21, 2000Date of Patent: April 22, 2003Assignee: Samsung Electronics Co.Inventors: Soo-cheol Lee, Jong-hyon Ahn, Kyoung-mok Son, Heon-jong Shin, Hyae-ryoung Lee, Young-pill Kim, Moo-jin Jung, Son-jong Wang, Jae-Cheol Yoo
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Patent number: 6541328Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which suicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.Type: GrantFiled: November 2, 2001Date of Patent: April 1, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-man Whang, Hyung-moo Park, Dong-cho Maeng, Hyae-Ryoung Lee, Ho-woo Park
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Patent number: 6465337Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart conductive layers and an array of spaced apart insulating islands in the third continuous conductive layer that extend therethrough such that sidewalls of the insulating islands are surrounded by the third continuous conductive layer. A fourth continuous conductive layer also may be provided between the third continuous conductive layer and the second conductive layer and a second array of spaced apart insulating islands may be provided in the fourth continuous conductive layer, that extend therethrough, such that sidewalls of the insulating islands are surrounded by the fourth continuous conductive layer.Type: GrantFiled: September 18, 2000Date of Patent: October 15, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-cheol Lee, Jong-hyon Ahn, Hyae-ryoung Lee
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Publication number: 20020115258Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which silicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.Type: ApplicationFiled: November 2, 2001Publication date: August 22, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-man Whang, Hyung-moo Park, Dong-cho Maeng, Hyae-Ryoung Lee, Ho-woo Park
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Publication number: 20010009802Abstract: Multilayer bonding pads for integrated circuits include first and second spaced apart conductive patterns and a dielectric layer therebetween. A closed conductive pattern is included in the dielectric layer that electrically connects the first and second spaced apart patterns. The closed conductive pattern encloses an inner portion of the dielectric layer and is enclosed by an outer portion of the dielectric layer. The closed conductive pattern may be a circular, elliptical, polygonal or other conductive pattern. A second closed conductive pattern may also be included in the inner portion of the dielectric layer, electrically connecting the first and second spaced apart conductive patterns. An open conductive pattern having end points, may also be included in the dielectric layer. The open conductive pattern may be included in the inner portion of the dielectric layer, in the outer portion of the dielectric layer or both.Type: ApplicationFiled: March 6, 2001Publication date: July 26, 2001Inventor: Hyae-Ryoung Lee
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Publication number: 20010002722Abstract: Disclosed is a capacitor of semiconductor integrated circuit and a method for fabricating the same by which characteristic of a capacitor and bit resolution can be improved to thereby obtain an improved analogue device of high accuracy. The capacitor of semiconductor integrated circuit includes a conductive lower electrode formed on a predetermined portion of an insulating substrate, an insulating layer formed on the insulating substrate including the conductive lower electrode and provided with a via hole so that the surface of the lower electrode is exposed in its predetermined portion, a dielectric layer formed on the insulating layer and in the via hole, and an conductive upper electrode formed on the predetermined portion of the dielectric layer including the via hole to have a piled structure such as “conductive plug/conductive layer pattern”.Type: ApplicationFiled: December 8, 2000Publication date: June 7, 2001Inventors: Hyae-Ryoung Lee, Sun-Il Yu, Dong-Woo Kim
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Publication number: 20010000928Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.Type: ApplicationFiled: December 21, 2000Publication date: May 10, 2001Inventors: Soo-Cheol Lee, Jong-Hyon Ahn, Kyoung-Mok Son, Heon-Jong Shin, Hyae-Ryoung Lee, Young-Pill Kim, Moo-Jin Jung, Son-Jong Wang, Jae-Cheol Yoo
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Patent number: 6222270Abstract: Multilayer bonding pads for integrated circuits include first and second spaced apart conductive patterns and a dielectric layer therebetween. A closed conductive pattern is included in the dielectric layer that electrically connects the first and second spaced apart patterns. The closed conductive pattern encloses an inner portion of the dielectric layer and is enclosed by an outer portion of the dielectric layer. The closed conductive pattern may be a circular, elliptical, polygonal or other conductive pattern. A second closed conductive pattern may also be included in the inner portion of the dielectric layer, electrically connecting the first and second spaced apart conductive patterns. An open conductive pattern having end points, may also be included in the dielectric layer. The open conductive pattern may be included in the inner portion of the dielectric layer, in the outer portion of the dielectric layer or both.Type: GrantFiled: June 24, 1998Date of Patent: April 24, 2001Assignee: Samsung Electronics Co., Ltd.Inventor: Hyae-ryoung Lee
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Patent number: 6184551Abstract: Disclosed is a capacitor of semiconductor integrated circuit and a method for fabricating the same by which characteristic of a capacitor and bit resolution can be improved to thereby obtain an improved analogue device of high accuracy. The capacitor of semiconductor integrated circuit includes a conductive lower electrode formed on a predetermined portion of an insulating substrate, an insulating layer formed on the insulating substrate including the conductive lower electrode and provided with a via hole so that the surface of the lower electrode is exposed in its predetermined portion, a dielectric layer formed on the insulating layer and in the via hole, and an conductive upper electrode formed on the predetermined portion of the dielectric layer including the via hole to have a piled structure such as “conductive plug/conductive layer pattern”.Type: GrantFiled: October 22, 1998Date of Patent: February 6, 2001Assignee: Samsung Electronics Co., LtdInventors: Hyae-Ryoung Lee, Sun-Il Yu, Dong-Woo Kim
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Patent number: 6163074Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart conductive layers and an array of spaced apart insulating islands in the third continuous conductive layer that extend therethrough such that sidewalls of the insulating islands are surrounded by the third continuous conductive layer. A fourth continuous conductive layer also may be provided between the third continuous conductive layer and the second conductive layer and a second array of spaced apart insulating islands may be provided in the fourth continuous conductive layer, that extend therethrough, such that sidewalls of the insulating islands are surrounded by the fourth continuous conductive layer.Type: GrantFiled: September 1, 1999Date of Patent: December 19, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-cheol Lee, Jong-hyon Ahn, Hyae-ryoung Lee