Abstract: A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.

Abstract: A method and device for controlling commands used for a flash memory are provided. The method includes, substantially reducing usage of a central processing unit (CPU) and a bus, when controlling the flash memory, by receiving information on at least one command currently stored in a system memory, receiving a command represented by the received information from the system memory, and generating an interrupt representing that all the commands are received, when receiving of substantially all the commands represented by the received information is completed.

Abstract: An apparatus for reproducing contents includes a reading unit which reads at least one of a plurality of reproduction setting information and at least one of a plurality of contents from a mobile recording medium, a control unit which analyzes the at least one of the plurality of reproduction setting information and sets a reproduction environment to reproduce the contents recorded on the mobile recording medium based on the analyzed at least one of the plurality of reproduction setting information, and a reproduction unit which reproduces the at least one of the plurality of contents based on the set reproduction environment.

Abstract: A command scheduling method and apparatus for reducing the complexity of a virtual file system embodied in a nonvolatile data storage device and performing efficient interleaving by setting a preparation phase of a command schedule in the virtual file system embodied in the nonvolatile data storage device is provided. The method includes setting a preparation phase in which a plurality of metadata commands for data management are executed, and if the plurality of metadata commands are completely executed in the preparation phase, executing data read/write commands. Accordingly, by simplifying the scheduling structure of the virtual file system (FTL), code size and resource use can be reduced. In addition, by performing exact interleaving, burst data transmission between a host and a memory storage device can be achieved even without using a large capacity buffer.

Abstract: A method and apparatus are provided for programming a non-volatile data storage device, in which a fast write operation can be performed using a plurality of page buffers included in the non-volatile data storage device when the write operation is performed in a way of using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices. The method includes programming data in a memory cell array included in the non-volatile data storage device using a page buffer selected from among a plurality of page buffers included in the non-volatile data storage device and performing a setup operation for loading data using another page buffer, which is different from the page buffer selected during the programming.

Abstract: The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.

Abstract: An apparatus and method of controlling data transmission between a NAND flash memory and a central processing unit using a direct memory access (DMA) method. The apparatus includes: a register storing an operating command from the central processing unit and information related to the operating command; a boot memory storing a boot code for initializing a system; a direct memory access (DMA) controller transmitting data stored in the NAND flash memory to a main memory without passing through the central processing unit; and a state machine controlling the NAND flash memory controlling apparatus. Accordingly, data transmission speed is increased, chip memory size is decreased, and booting time is reduced.

Abstract: The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.