Patents by Inventor Hye-Hyeon BYEON
Hye-Hyeon BYEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903209Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.Type: GrantFiled: June 24, 2022Date of Patent: February 13, 2024Assignee: SK hynix Inc.Inventors: Hye-Hyeon Byeon, Sang-Deok Kim, Il-Young Kwon, Tae-Hong Gwon, Jin-Ho Bin
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Publication number: 20230337430Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.Type: ApplicationFiled: June 22, 2023Publication date: October 19, 2023Applicant: SK hynix Inc.Inventors: Jin-Ho BIN, Il-Young KWON, Tae-Hong GWON, Hye-Hyeon BYEON
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Patent number: 11729979Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.Type: GrantFiled: November 24, 2021Date of Patent: August 15, 2023Assignee: SK hynix Inc.Inventors: Jin-Ho Bin, Il-Young Kwon, Tae-Hong Gwon, Hye-Hyeon Byeon
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Publication number: 20220336491Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.Type: ApplicationFiled: June 24, 2022Publication date: October 20, 2022Applicant: SK hynix Inc.Inventors: Hye-Hyeon BYEON, Sang-Deok KIM, Il-Young KWON, Tae-Hong GWON, Jin-Ho BIN
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Patent number: 11404432Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.Type: GrantFiled: December 6, 2019Date of Patent: August 2, 2022Assignee: SK hynix Inc.Inventors: Hye-Hyeon Byeon, Sang-Deok Kim, Il-Young Kwon, Tae-Hong Gwon, Jin-Ho Bin
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Patent number: 11393839Abstract: Disclosed is a semiconductor device with improved electrical characteristics and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked on a substrate, forming a first through portion in the alternating stack, etching first portions of the sacrificial layers through the first through portion, to form lateral recesses between the dielectric layers, forming charge trapping layers isolated in the lateral recesses, forming a second through portion by etching the alternating stack in which second portions of the sacrificial layers remain, removing the second portions of the sacrificial layers through the second through portion, to form gate recesses that expose non-flat surfaces of the charge trapping layers, flattening the non-flat surfaces of the charge trapping layers, and forming a gate electrode that fills the gate recesses.Type: GrantFiled: May 4, 2020Date of Patent: July 19, 2022Assignee: SK hynix Inc.Inventors: Jin-Ho Bin, Il-Young Kwon, Hye-Hyeon Byeon, Dong-Chul Yoo
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Publication number: 20220085069Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.Type: ApplicationFiled: November 24, 2021Publication date: March 17, 2022Applicant: SK hynix Inc.Inventors: Jin-Ho BIN, Il-Young KWON, Tae-Hong GWON, Hye-Hyeon BYEON
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Patent number: 11239251Abstract: A method of manufacturing a non-volatile memory device includes forming a gate insulation layer on a semiconductor substrate having a source layer. The method also includes forming a silicon nitride layer having a buffer-treated upper surface on the gate insulation layer, wherein the buffer-treated upper surface of the silicon nitride layer has a hardness higher than a hardness of the silicon nitride layer. The method further includes forming a silicon oxide layer on the buffer-treated upper surface of the silicon nitride layer. The method additionally includes alternately forming additional silicon nitride layers and additional silicon oxide layers on the silicon oxide layer to form a stack structure.Type: GrantFiled: April 22, 2020Date of Patent: February 1, 2022Assignee: SK hynix Inc.Inventors: Hye Hyeon Byeon, Il Young Kwon, Jin Ho Bin
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Patent number: 11217602Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.Type: GrantFiled: December 11, 2019Date of Patent: January 4, 2022Assignee: SK hynix Inc.Inventors: Jin-Ho Bin, Il-Young Kwon, Tae-Hong Gwon, Hye-Hyeon Byeon
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Publication number: 20210151459Abstract: A method of manufacturing a non-volatile memory device includes forming a gate insulation layer on a semiconductor substrate having a source layer. The method also includes forming a silicon nitride layer having a buffer-treated upper surface on the gate insulation layer, wherein the buffer-treated upper surface of the silicon nitride layer has a hardness higher than a hardness of the silicon nitride layer. The method further includes forming a silicon oxide layer on the buffer-treated upper surface of the silicon nitride layer. The method additionally includes alternately forming additional silicon nitride layers and additional silicon oxide layers on the silicon oxide layer to form a stack structure.Type: ApplicationFiled: April 22, 2020Publication date: May 20, 2021Applicant: SK hynix Inc.Inventors: Hye Hyeon BYEON, Il Young KWON, Jin Ho BIN
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Publication number: 20210098485Abstract: Disclosed is a semiconductor device with improved electrical characteristics and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked on a substrate, forming a first through portion in the alternating stack, etching first portions of the sacrificial layers through the first through portion, to form lateral recesses between the dielectric layers, forming charge trapping layers isolated in the lateral recesses, forming a second through portion by etching the alternating stack in which second portions of the sacrificial layers remain, removing the second portions of the sacrificial layers through the second through portion, to form gate recesses that expose non-flat surfaces of the charge trapping layers, flattening the non-flat surfaces of the charge trapping layers, and forming a gate electrode that fills the gate recesses.Type: ApplicationFiled: May 4, 2020Publication date: April 1, 2021Applicant: SK hynix Inc.Inventors: Jin-Ho BIN, Il-Young KWON, Hye-Hyeon BYEON, Dong-Chul YOO
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Publication number: 20210028187Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.Type: ApplicationFiled: December 6, 2019Publication date: January 28, 2021Applicant: SK hynix Inc.Inventors: Hye-Hyeon BYEON, Sang-Deok KIM, Il-Young KWON, Tae-Hong GWON, Jin-Ho BIN
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Publication number: 20200388631Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.Type: ApplicationFiled: December 11, 2019Publication date: December 10, 2020Applicant: SK hynix Inc.Inventors: Jin-Ho BIN, Il-Young KWON, Tae-Hong GWON, Hye-Hyeon BYEON