Patents by Inventor Hye-In Choi

Hye-In Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230218675
    Abstract: The present invention relates to exosomes isolated from dermal papilla progenitor cells, specifically, the exosomes isolated from the dermal papilla progenitor cells which are excellent in prevention, improvement and treatment of hair loss (alopecia) and are also excellent in terms of skin improvement and wound healing effects, as well as various uses thereof.
    Type: Application
    Filed: June 5, 2020
    Publication date: July 13, 2023
    Inventors: Sung Ha KIM, Hye-In CHOI
  • Patent number: 10588906
    Abstract: Provided herein is a method of preventing hair loss or promoting hair growth, the method including administering an effective amount of a PDE 3 inhibitor. More particularly, when the method of the present disclosure is used, an excellent hair loss prevention or hair growth promotion effect is obtained by inhibiting the activity of PDE 3.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 17, 2020
    Assignee: SEOUL NATIONAL UNIVERSITY HOSPITAL
    Inventors: Ohsang Kwon, Hye-In Choi, Seong Jin Jo, Kyu Han Kim
  • Publication number: 20190046528
    Abstract: Provided herein is a method of preventing hair loss or promoting hair growth, the method including administering an effective amount of a PDE 3 inhibitor. More particularly, when the method of the present disclosure is used, an excellent hair loss prevention or hair growth promotion effect is obtained by inhibiting the activity of PDE 3.
    Type: Application
    Filed: July 25, 2018
    Publication date: February 14, 2019
    Applicant: SEOUL NATIONAL UNIVERSITY HOSPITAL
    Inventors: Ohsang KWON, Hye-In CHOI, Seong Jin JO, Kyu Han KIM
  • Patent number: 8993343
    Abstract: The present invention relates to an anti-inflammatory composition using the antibody specifically binding to CD93 or its soluble fragment, and a diagnostic method and a diagnostic kit for inflammatory disease using CD93 or its soluble fragment specific antibody or aptamer.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: March 31, 2015
    Assignee: Korea Research Institute of Bioscience and Biotechnology
    Inventors: Young Woo Park, Jae Won Jeon, Joon-Goo Jung, Hye In Choi, Myung-ho Sohn, Ho youn Kim, Mi-La Cho, Young-Soon Jang, Ji-Hun Moon, Ji Hyun Park
  • Publication number: 20120039911
    Abstract: The present invention relates to an anti-inflammatory composition using the antibody specifically binding to CD93 or its soluble fragment, and a diagnostic method and a diagnostic kit for inflammatory disease using CD93 or its soluble fragment specific antibody or aptamer.
    Type: Application
    Filed: January 28, 2009
    Publication date: February 16, 2012
    Applicant: Korea Research Institute of Bioscience and Biotech
    Inventors: Young Woo Park, Jae Won Jeon, Joon-Goo Jung, Hye In Choi, Myung-ho Sohn, Ho youn Kim, Mi-La Cho, Young-Soon Jang, Ji-Hun Moon, Ji Hyun Park
  • Patent number: 7257754
    Abstract: A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 14, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moo-Sung Chae, Hye-In Choi
  • Publication number: 20070152723
    Abstract: A delay-locked loop (DLL) circuit capable of decreasing power consumption is provided. A DLL circuit includes a delay line, an output buffer, a replica circuit, a phase detector, a shift register and a replica control circuit. The delay line delays an external clock signal for a determined time to generate a first signal. The output buffer buffers the first signal to generate an internal clock signal. The replica circuit delays the first signal for a determined time to generate a feedback signal. The phase detector compares the feedback signal with the external clock signal to generate a shift control signal. The shift register performs a shifting operation based on the shift control signal to generate the plurality of delay control bits. The replica control circuit generates a replica control signal based on the external clock signal and a lock signal, to control the replica circuit.
    Type: Application
    Filed: December 7, 2006
    Publication date: July 5, 2007
    Inventors: Ji-Hyun Ahn, Jae-Ki Yoo, Hye-In Choi
  • Publication number: 20050108607
    Abstract: A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.
    Type: Application
    Filed: September 29, 2004
    Publication date: May 19, 2005
    Inventors: Moo-Sung Chae, Hye-In Choi