Patents by Inventor Hye Jeong CHEON

Hye Jeong CHEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497716
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 3, 2019
    Assignee: SK hynix Inc.
    Inventors: In Su Park, Ki Hong Lee, Hye Jeong Cheon
  • Publication number: 20180323211
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: In Su PARK, Ki Hong LEE, Hye Jeong CHEON
  • Patent number: 10050056
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: August 14, 2018
    Assignee: SK Hynix Inc.
    Inventors: In Su Park, Ki Hong Lee, Hye Jeong Cheon
  • Publication number: 20180097013
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: In Su PARK, Ki Hong LEE, Hye Jeong CHEON
  • Patent number: 9859299
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 2, 2018
    Assignee: SK Hynix Inc.
    Inventors: In Su Park, Ki Hong Lee, Hye Jeong Cheon
  • Publication number: 20170323899
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Application
    Filed: September 28, 2016
    Publication date: November 9, 2017
    Inventors: In Su PARK, Ki Hong LEE, Hye Jeong CHEON