Patents by Inventor Hye-Jung KWON
Hye-Jung KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071475Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: ApplicationFiled: October 24, 2023Publication date: February 29, 2024Inventors: YOON-JOO EOM, SEUNGJUN BAE, HYE JUNG KWON, YOUNG-JU KIM
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Patent number: 11862234Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: GrantFiled: December 1, 2021Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Seungjun Bae, Hye Jung Kwon, Young-Ju Kim
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Publication number: 20220093161Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Inventors: YOON-JOO EOM, SEUNGJUN BAE, HYE JUNG KWON, YOUNG-JU KIM
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Patent number: 11195571Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: GrantFiled: September 20, 2018Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Joo Eom, Seungjun Bae, Hye Jung Kwon, Young-Ju Kim
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Patent number: 11024364Abstract: There are provided a sense amplifier for sensing a multilevel cell and a memory device including the same. The sense amplifier is configured to sense the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data a cell voltage stored in a memory cell as the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data. The sense amplifier senses the MSB of the 2-bit data in a state in which a bit line is electrically disconnected from a holding bit line of the sense amplifier and senses the LSB of the 2-bit data in a state in which the cell bit line is electrically connected to the holding bit line. The sense amplifier is configured to equalize a pair of bit lines of the sense amplifier before sensing the MSB and the LSB of the 2-bit data. The sense amplifier is configured to restore to the memory cell the cell voltage corresponding to the sensed MSB and LSB of the 2-bit data.Type: GrantFiled: August 29, 2019Date of Patent: June 1, 2021Inventors: Young-Hun Seo, Dong-Il Lee, Hye-Jung Kwon
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Patent number: 10969420Abstract: A test circuit includes a first logic gate that receives a test signal or a first voltage, a second logic gate that receives the test signal, a third logic gate that receives an output of the first logic gate, an output of the second logic gate, or a second voltage, a fourth logic gate that receives the output of the first logic gate or the output of the second logic gate, and a power circuit that prevents the second and fourth logic gates from being driven by supplying power to the second and fourth logic gates when the first logic gate receives the first voltage and the third logic gate receives the second voltage.Type: GrantFiled: June 29, 2018Date of Patent: April 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye Jung Kwon, Seungjun Bae
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Patent number: 10734043Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.Type: GrantFiled: August 3, 2018Date of Patent: August 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Ju Kim, Dong-Seok Kang, Hye Jung Kwon, Byungchul Kim, Seungjun Bae
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Patent number: 10666467Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.Type: GrantFiled: August 22, 2018Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye Jung Kwon, Seungjun Bae, Yongjae Lee, Young-Sik Kim, Young-Ju Kim, Suyeon Doo, Yoon-Joo Eom
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Patent number: 10649849Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.Type: GrantFiled: March 28, 2018Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hun Kim, Su-Yeon Doo, Dong-Seok Kang, Hye-Jung Kwon, Young-Ju Kim
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Publication number: 20200143869Abstract: There are provided a sense amplifier for sensing a multilevel cell and a memory device including the same. The sense amplifier is configured to sense the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data a cell voltage stored in a memory cell as the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data. The sense amplifier senses the MSB of the 2-bit data in a state in which a bit line is electrically disconnected from a holding bit line of the sense amplifier and senses the LSB of the 2-bit data in a state in which the cell bit line is electrically connected to the holding bit line. The sense amplifier is configured to equalize a pair of bit lines of the sense amplifier before sensing the MSB and the LSB of the 2-bit data. The sense amplifier is configured to restore to the memory cell the cell voltage corresponding to the sensed MSB and LSB of the 2-bit data.Type: ApplicationFiled: August 29, 2019Publication date: May 7, 2020Inventors: YOUNG-HUN SEO, Dong-Il Lee, Hye-Jung Kwon
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Patent number: 10388399Abstract: Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.Type: GrantFiled: December 21, 2017Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-jung Kwon, Kwang-il Park, Seung-jun Bae, Eun-sung Seo
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Publication number: 20190180797Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.Type: ApplicationFiled: August 3, 2018Publication date: June 13, 2019Inventors: YOUNG-JU KIM, DONG-SEOK KANG, HYE JUNG KWON, BYUNGCHUL KIM, SEUNGJUN BAE
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Publication number: 20190164594Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.Type: ApplicationFiled: September 20, 2018Publication date: May 30, 2019Inventors: YOON-JOO EOM, SEUNGJUN BAE, HYE JUNG KWON, YOUNG-JU KIM
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Patent number: 10305457Abstract: A voltage trimming circuit includes a comparator, a code generator, nonvolatile storage device, a switch circuit, and a voltage generator. The comparator compares a reference voltage with a feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on the comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts up codes to increase the feedback voltage, from among the plurality of trimming codes and maintains down codes to decrease the feedback voltage, from among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down codes and maintains the up codes at an initial value.Type: GrantFiled: December 15, 2017Date of Patent: May 28, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hye Jung Kwon, Younghun Seo
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Publication number: 20190158320Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.Type: ApplicationFiled: August 22, 2018Publication date: May 23, 2019Inventors: Hye Jung Kwon, Seungjun Bae, Yongjae Lee, Young-Sik Kim, Young-Ju Kim, Suyeon Doo, Yoon-Joo Eom
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Publication number: 20190137563Abstract: A test circuit includes a first logic gate that receives a test signal or a first voltage, a second logic gate that receives the test signal, a third logic gate that receives an output of the first logic gate, an output of the second logic gate, or a second voltage, a fourth logic gate that receives the output of the first logic gate or the output of the second logic gate, and a power circuit that prevents the second and fourth logic gates from being driven by supplying power to the second and fourth logic gates when the first logic gate receives the first voltage and the third logic gate receives the second voltage.Type: ApplicationFiled: June 29, 2018Publication date: May 9, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Hye Jung KWON, Seungjun BAE
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Publication number: 20190018737Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.Type: ApplicationFiled: March 28, 2018Publication date: January 17, 2019Inventors: YONG-HUN KIM, SU-YEON DOO, DONG-SEOK KANG, HYE-JUNG KWON, YOUNG-JU KIM
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Publication number: 20180358109Abstract: Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.Type: ApplicationFiled: December 21, 2017Publication date: December 13, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Hye-jung Kwon, Kwang-il PARK, Seung-jun BAE, Eun-sung SEO
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Publication number: 20180337663Abstract: A voltage trimming circuit includes a comparator, a code generator, nonvolatile storage device, a switch circuit, and a voltage generator. The comparator compares a reference voltage with a feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on the comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts up codes to increase the feedback voltage, from among the plurality of trimming codes and maintains down codes to decrease the feedback voltage, from among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down codes and maintains the up codes at an initial value.Type: ApplicationFiled: December 15, 2017Publication date: November 22, 2018Inventors: Hye Jung Kwon, Younghun Seo
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Patent number: D1017611Type: GrantFiled: June 26, 2023Date of Patent: March 12, 2024Assignee: Samsung Display Co., Ltd.Inventors: Ho Jung Lee, Kyung Hyun Ko, Yong Woo Koo, Jun Il Kwon, Pablo Kim, Young-Su Kim, Jun Woo Kim, Hoon Kim, Hye Suk An, Hyun Joo Lee, Ki Ho Lim