Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Abstract: Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device.

Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Abstract: Provided are methods of manufacturing semiconductor devices. The methods may include forming a first insulation layer on a semiconductor substrate, forming a groove by selectively etching the first insulation layer, filling the groove with a copper-based conductive layer, depositing a cobalt-based capping layer on the copper-based conductive layer by electroless plating, and cleansing the first insulation layer and the cobalt-based capping layer using a basic cleansing solution.

Abstract: Methods of forming field effect transistors include forming a metal alloy gate electrode (e.g., aluminum alloy) containing about 0.5 to about 1.0 atomic percent silicon, on a substrate, and electroless plating an electrically conductive gate protection layer directly on at least a portion of an upper surface of the metal alloy gate electrode. A gate dielectric layer may be formed on the substrate. This gate dielectric layer may have a dielectric constant greater than a dielectric constant of silicon dioxide. The forming of the metal alloy gate electrode may include forming a metal alloy gate electrode directly on an upper surface of the gate dielectric layer.

Abstract: Provided are methods of manufacturing semiconductor devices. The methods may include forming a first insulation layer on a semiconductor substrate, forming a groove by selectively etching the first insulation layer, filling the groove with a copper-based conductive layer, depositing a cobalt-based capping layer on the copper-based conductive layer by electroless plating, and cleansing the first insulation layer and the cobalt-based capping layer using a basic cleansing solution.

Abstract: Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device.

Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.