Abstract: The present technology relates to an electronic device. A memory controller according to the present technology may include a host interface controller, a plurality of buffers, and a memory operation controller. The host interface controller may sequentially generate a plurality of commands based on a request received from a host. The plurality of buffers may store the plurality of commands according to command attributes. The memory operation controller may compare a sequence number of a target command stored in a target buffer among the plurality of buffers with a sequence number of a standby command stored in remaining buffers, and may determine a process of the target command and a process of the standby command based on a comparison. wherein a buffer satisfying a flush condition among the plurality of buffers is selected as the target buffer.

Abstract: A data storage apparatus is provided to include a storage including a main data region for storing first data and a spare region for storing second data indicating attributes of the first data; and a controller in communication with a host and configured to control the storage based on a request from the host, wherein the controller comprises: a first error check and correction (ECC) engine configured to perform an error correction on the first data stored in the main data region of the storage; and a second ECC engine configured to perform an error correction on the second data stored in the spare region of the storage.

Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

Abstract: Embodiments of the disclosure relate to a memory system, a memory controller and a meta-information storage device. By providing a memory device configured to store mapping information between a logical address and a physical address, a memory controller configured to control the memory device and control a memory area in which mapping segments including some of the mapping information are stored and a meta-information storage device configured to store meta-information on the memory area, it is possible to provide a memory system, a memory controller and a meta-information storage device capable of processing a command received from a host as quickly as possible even when an SPO occurs.

Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.

Abstract: A memory controller for controlling a memory device which stores logical-to-physical (L2P) segments includes a map data storage and a map manager. The map data storage stores a plurality of physical-to-logical (P2L) segments including mapping information between a physical address of the memory device in which write data is to be stored and a logical address received from a host, in response to a write request received from the host. The map manager updates the L2P segments stored in the memory device, based on target P2L segments corresponding to a write command provided to the memory device, which have a higher priority than the other P2L segments among the plurality of P2L segments. Each of L2P segments includes mapping information between a logical address and a physical address of data stored in the memory device.

Abstract: A memory system is provided to include memory devices and a controller including cores controlling the memory devices, respectively. The controller determines whether to perform a global wear-leveling operation based on a write count of the plurality of memory devices corresponding to each of the plurality of cores, performs a barrier operation for a request from a host when the global wear-leveling operation is determined to be performed, updates mapping information for mapping a core to memory device information by swapping the mapping information between different cores based on the write count of each of the plurality of cores and closes an open block assigned to each of the plurality of cores and then assigning a new open block to each of the plurality of cores based on the updated mapping information.

Abstract: A memory controller may include a map cache configured to store one or more of a plurality of map data sub-segments respectively corresponding to a plurality of sub-areas included in each of the plurality of areas, and a map data manager configured to generate information about a map data sub-segment to be provided to a host and which is determined based on a read count for the memory device, and generate information about a map data segment to be deleted from the host and which is determined based on the read count for the memory device and a memory of the host.

Abstract: A memory system is provided to include memory devices and a controller including cores controlling the memory devices, respectively. The controller determines whether to perform a global wear-leveling operation based on a write count of the plurality of memory devices corresponding to each of the plurality of cores, performs a barrier operation for a request from a host when the global wear-leveling operation is determined to be performed, updates mapping information for mapping a core to memory device information by swapping the mapping information between different cores based on the write count of each of the plurality of cores and closes an open block assigned to each of the plurality of cores and then assigning a new open block to each of the plurality of cores based on the updated mapping information.

Abstract: A memory system includes a memory device and a controller. The memory device includes at least one open memory block. The controller is configured to program data input along with write requests from an external device in the at least one open memory block, determine a storage mode regarding map data based on a type of the write requests, and perform a map update based on the map data. The controller is further configured to determine a timing for performing the map update is determined based on the storage mode and the type of write requests.

Abstract: A memory system, a memory controller and a method for operating the memory system. The memory system manages a hot data pool and a cold data pool, each of which includes at least one among a plurality of memory blocks, writes read only data to the cold data pool, and controls the hot data pool and the cold data pool in garbage collection and wear leveling, thereby classifying data, less frequently updated, into cold data and improving the performance of garbage collection and wear leveling.

Abstract: A memory system includes a storage medium configured to store map data and a controller configured to perform a host map cache management operation so that the map data is stored in a host map cache included in a host device in response to the activation of a host map cache management function and configured to selectively deactivate the host map cache management function.

Abstract: A memory system, a memory controller and an operating method are disclosed. By determining a time for garbage collection, based on information for a write command group including a plurality of write commands inputted from a host, it is possible to minimize a time in which processing a command transmitted from the host is delayed due to garbage collection, and ensure stable write performance.

Abstract: In accordance with an embodiment of the present disclosure, a method of a controller for controlling a nonvolatile memory device including a plurality of data storage regions may include: determining, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, changing a logical address mapped to the first physical address from the first logical address to the second logical address and invalidating the first logical address.

Abstract: A data storage apparatus includes a storage device; a controller to control data input and output operations of the storage device; and a swap memory provided in an outside of the controller, wherein the controller includes a thread manager to perform a preparation operation on a first thread included in a task in response to a request for processing the task, request the storage device to process the first thread on which the preparation operation has been performed, perform a preparation operation on at least one subsequent thread following the first thread while the storage device processes the first thread, and store context data of the first thread and the at least one subsequent thread in the swap memory, wherein the task includes the first thread and the at least one subsequent thread, and the preparation operation includes an address mapping operation.

Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.

Abstract: A data storage apparatus may include a storage and a controller configured to control the storage in response to a request of a host, wherein the controller comprises a map data management component configured to: generate one or more map segments, each of which includes a plurality of pieces of map data, which represent mapping information between logical addresses of the host and physical addresses of the storage; store the map segments in the storage; group the map data in each of the map segments into groups of one or more sub-segments; and load the map data of each of the map segments in units of the sub-segments.

Abstract: The present technology relates to an electronic device. A memory controller according to the present technology has improved map update performance. The memory controller controls a memory device that stores logical to physical map data indicating a mapping relationship between a logical address and a physical address of data. The memory controller includes a map data storage and a map data manager. The map data storage stores physical to logical (P2L) map data generated based on a logical address corresponding to a request received from a host. The map data manager performs a map update operation for the L2P map data by using some of an entire P2L map data stored in the map data storage, according to an amount of the P2L map data stored in the map data storage.

Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes a read counter configured to store a block read count value of a super block and memory blocks within a non-super block as a status information in an internal memory by counting a number of times that a read operation is performed on the memory blocks; and a super block manager configured to: store a super block reclaim trigger reference and a non-super block reclaim trigger reference, which is set for the super block and the non-super block, as the status information in the internal memory, divide data stored in the memory blocks into hot data and cold data according to the block read count value, and copy the hot data in the non-super block to the super block according to the status information.

Abstract: A memory system, a memory controller and an operating method are disclosed. By determining a time for garbage collection, based on information for a write command group including a plurality of write commands inputted from a host, it is possible to minimize a time in which processing a command transmitted from the host is delayed due to garbage collection, and ensure stable write performance.