Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer and a second hard mask layer over an etch target layer, forming second hard mask patterns by etching the second hard mask layer, wherein an etching profile of the second hard mask layer has a positive slope, and etching the first hard mask layer and the etch target layer using the second hard mask patterns as an etch mask.

Abstract: A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trench patterns.

Abstract: A method for fabricating a nonvolatile memory device includes repeatedly stacking a stacked structure over a substrate to form a multi-stacked structure, wherein the stacked structure includes a conductive layer and an insulation layer, forming a photoresist pattern over the multi-stacked structure, first-etching an uppermost stacked structure of the multi-stacked structure using the photoresist pattern as an etch barrier, second-etching a resultant structure formed by the first-etching through the use of a breakthrough etching, slimming the photoresist pattern to form a slimmed photoresist pattern, and third-etching the uppermost stacked structure using the slimmed photoresist pattern as an etch barrier and, at the same time, etching a stacked structure disposed under the uppermost stacked structure and exposed by the first-etching.

Abstract: A charge trap-type non-volatile memory device, and related method, includes forming over a substrate a tunnel insulating layer, a charge trapping layer, a dielectric layer, and a conductive layer for a gate electrode; forming a gate electrode by selectively etching the conductive layer for the gate electrode; forming a spacer including a first spacer and a second spacer on a sidewall of the gate electrode, the second spacer being formed of material different from that of the first spacer; and etching the dielectric layer and the charge trapping layer by using the spacer as an etching barrier, thereby preventing an attack to the gate electrode when etching the charge trapping layer and thus enhancing reliability and stability of transistors. In addition, in one or more embodiments, a sidewall of the charge trapping layer pattern is formed vertically, thereby preventing formation of a tail and an attack to the substrate.

Abstract: A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trench patterns.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer and a second hard mask layer over an etch target layer, forming second hard mask patterns by etching the second hard mask layer, wherein an etching profile of the second hard mask layer has a positive slope, and etching the first hard mask layer and the etch target layer using the second hard mask patterns as an etch mask.