Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

Abstract: A memory package includes a plurality of memory chips stacked on a package substrate. A logic chip is disposed between the plurality of memory chips and the package substrate. The logic chip is configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips. An intermediate chip is connected to the plurality of vias. The intermediate chip is disposed between the plurality of memory chips and the logic chip, and is configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

Abstract: A memory package includes a plurality of memory chips stacked on a package substrate. A logic chip is disposed between the plurality of memory chips and the package substrate. The logic chip is configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips. An intermediate chip is connected to the plurality of vias. The intermediate chip is disposed between the plurality of memory chips and the logic chip, and is configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Abstract: A memory device including an interposer including a first plurality of paths and a second plurality of paths, a first memory die attached to a first surface of the interposer, the first memory die including a first physical layer connected to the first plurality of paths, the first physical layer being attached to a first surface of the interposer, and a second memory die attached to a second surface of the interposer, the second memory die including a second physical layer connected to the second plurality of paths, the second physical layer being attached to a second surface of the interposer, the second physical layer not interfering with the first physical layer in a plan view may be provided.

Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.

Abstract: A three-dimensional (3D) inductor structure comprising: a first semiconductor die including: a first conductive pattern; and a second conductive pattern spaced apart from the first conductive pattern; a second semiconductor die stacked on the first semiconductor die, the second semiconductor die including: a third conductive pattern; a fourth conductive pattern spaced apart from the third conductive pattern; a first through-substrate via (TSV) penetrating the second semiconductor die and electrically connecting the first conductive pattern with the third conductive pattern; and a second TSV penetrating the second semiconductor die and electrically connecting the second conductive pattern with the fourth conductive pattern, and a first conductive connection pattern included in the first semiconductor die and electrically connecting a first end of the first conductive pattern with a first end of the second conductive pattern, or included in the second semiconductor die and electrically connecting a first end of

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.