Patents by Inventor Hye-Soo Shin
Hye-Soo Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240126074Abstract: The present disclosure provides a waveguide display apparatus. The waveguide waveguide display apparatus of the present disclosure is a waveguide display apparatus for correcting curved surface reflection distortion, the waveguide display apparatus including a waveguide for guiding light inputted from the outside; a first diffractive optical element disposed at the waveguide, and diffracting the light inputted from the outside to the inside of the waveguide; and a second diffractive optical element disposed at the waveguide, and diffracting the light guided by the waveguide to output a plurality of diffracted lights in a direction of a curved surface reflector located outside, wherein the second diffractive optical element has a structure of a diffraction grating corresponding to a curvature of the curved surface reflector such that the diffracted lights are reflected at different locations of the curved surface reflector in directions parallel to each other.Type: ApplicationFiled: September 30, 2022Publication date: April 18, 2024Applicant: LG Chem, Ltd.Inventors: Jae Jin Kim, Bo Ra Jung, Hye Won Hwang, Yeon Jae Yoo, Joon Young Lee, Bu Gon Shin, Min Soo Song
-
Patent number: 9607852Abstract: Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively.Type: GrantFiled: April 24, 2014Date of Patent: March 28, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-Hoon Lee, Sang-Wook Seo, Hye-Soo Shin
-
Patent number: 9355204Abstract: A method of decomposing a design layout for a double patterning process is provided. The method includes changing, by a computing system, a design layout of a first polygon type to a design layout of a curved polygon type; coloring the design layout of the curved polygon type; generating stitching shapes for preventing acute corners in stitching areas of the colored design layout of the curved polygon type; separating the design layout including the stitching shapes for preventing the acute corners into separated design layouts of curved polygon type according to colors; and changing the separated design layouts of the curved polygon type to design layouts of a second polygon type.Type: GrantFiled: August 20, 2014Date of Patent: May 31, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Wook Seo, Jeong-Hoon Lee, Hye-Soo Shin
-
Publication number: 20150227666Abstract: A method of decomposing a design layout for a double patterning process is provided. The method includes changing, by a computing system, a design layout of a first polygon type to a design layout of a curved polygon type; coloring the design layout of the curved polygon type; generating stitching shapes for preventing acute corners in stitching areas of the colored design layout of the curved polygon type; separating the design layout including the stitching shapes for preventing the acute corners into separated design layouts of curved polygon type according to colors; and changing the separated design layouts of the curved polygon type to design layouts of a second polygon type.Type: ApplicationFiled: August 20, 2014Publication date: August 13, 2015Inventors: Sang-Wook Seo, Jeong-Hoon Lee, Hye-Soo Shin
-
Publication number: 20150011022Abstract: Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively.Type: ApplicationFiled: April 24, 2014Publication date: January 8, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-Hoon Lee, Sang-Wook Seo, Hye-Soo Shin
-
Patent number: 8426299Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.Type: GrantFiled: December 27, 2011Date of Patent: April 23, 2013Assignee: Samsung Electronics Co., LtdInventors: Joon-Sung Kim, Hye-Soo Shin, Mi-Youn Kim, Young-Soo Kim
-
Publication number: 20120164821Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.Type: ApplicationFiled: December 27, 2011Publication date: June 28, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Joon-Sung KIM, Hye-Soo SHIN, Mi-Youn KIM, Young-Soo KIM
-
Patent number: 7510952Abstract: A single crystalline structure includes a first insulation interlayer pattern, a first epitaxial layer pattern, a second insulation interlayer pattern, and a second epitaxial layer pattern. The first insulation interlayer pattern includes a contact hole that exposes a single crystalline seed. The first epitaxial layer pattern fills up the contact hole. The second insulation interlayer pattern is formed on the first insulation interlayer pattern and the first epitaxial layer pattern. The second insulation interlayer pattern has a trench that partially exposes the first epitaxial layer pattern and has an end disposed over an upper surface of the first epitaxial layer pattern. The second epitaxial layer pattern fills up the trench. Thus, voids are not generated in the second epitaxial layer pattern and a semiconductor device having the single crystalline structure exhibits improved reliability.Type: GrantFiled: January 18, 2006Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Hye-Soo Shin
-
Patent number: 7097949Abstract: A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.Type: GrantFiled: October 17, 2003Date of Patent: August 29, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hyun Kim, Moon-Hyun Yoo, Jeong-Lim Nam, Yoo-Hyon Kim, Chul-Hong Park, Soo-Han Choi, Young-Chan Ban, Hye-Soo Shin
-
Publication number: 20060157708Abstract: A single crystalline structure includes a first insulation interlayer pattern, a first epitaxial layer pattern, a second insulation interlayer pattern, and a second epitaxial layer pattern. The first insulation interlayer pattern includes a contact hole that exposes a single crystalline seed. The first epitaxial layer pattern fills up the contact hole. The second insulation interlayer pattern is formed on the first insulation interlayer pattern and the first epitaxial layer pattern. The second insulation interlayer pattern has a trench that partially exposes the first epitaxial layer pattern and has an end disposed over an upper surface of the first epitaxial layer pattern. The second epitaxial layer pattern fills up the trench. Thus, voids are not generated in the second epitaxial layer pattern and a semiconductor device having the single crystalline structure exhibits improved reliability.Type: ApplicationFiled: January 18, 2006Publication date: July 20, 2006Inventor: Hye-Soo Shin
-
Publication number: 20050153539Abstract: A method of forming interconnection lines in a semiconductor device is disclosed. According to the method, a trench is formed in a semiconductor substrate and a scattered reflection layer is formed on the overall surface of the semiconductor substrate including the trench. The scattered reflection layer increases an optical energy reflection rate of a light source used in a photolithography process, thereby providing sufficient energy to completely expose photoresist used to form a photoresist pattern in the trench.Type: ApplicationFiled: December 16, 2004Publication date: July 14, 2005Inventors: Hye-Soo Shin, Do-Yul Yoo
-
Publication number: 20040091794Abstract: A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.Type: ApplicationFiled: October 17, 2003Publication date: May 13, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Hyun Kim, Moon-Hyun Yoo, Jeong-Lim Nam, Yoo-Hyon Kim, Chul-Hong Park, Soo-Han Choi, Young-Chan Ban, Hye-Soo Shin
-
Patent number: 6717272Abstract: A semiconductor device for reinforcing a substructure of a bond pad and a method for fabricating the same are provided. According to an embodiment, a semiconductor device for reinforcing a substructure of a bond pad comprises a semiconductor substrate and a substructure formed on the semiconductor substrate. The semiconductor device further includes an interlevel dielectric layer formed on the substructure. The interlevel dielectric layer includes a contact opening formed therein. The contact opening comprises a plurality of separate dots connected to each other. A contact plug is formed in the contact opening.Type: GrantFiled: February 26, 2003Date of Patent: April 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyuk Lee, Sa-Yoon Kang, Dong-Whee Kwon, Ji-Yong You, Hye-Soo Shin
-
Publication number: 20030178644Abstract: A semiconductor device for reinforcing a substructure of a bond pad and a method for fabricating the same are provided. According to an embodiment, a semiconductor device for reinforcing a substructure of a bond pad comprises a semiconductor substrate and a substructure formed on the semiconductor substrate. The semiconductor device further includes an interlevel dielectric layer formed on the substructure. The interlevel dielectric layer includes a contact opening formed therein. The contact opening comprises a plurality of separate dots connected to each other. A contact plug is formed in the contact opening.Type: ApplicationFiled: February 26, 2003Publication date: September 25, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-Hyuk Lee, Sa-Yoon Kang, Dong-Whee Kwon, Ji-Yong You, Hye-Soo Shin
-
Patent number: 6571384Abstract: A method of forming fine patterns in a semiconductor device through a double photo lithography process. A layer to be etched and a hard mask layer are sequentially formed on a semiconductor substrate. A first photo resist pattern is formed on the hard mask layer. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After the first photo resist pattern is removed, a second photo resist pattern is formed on the resultant structure. A second hard mask layer pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. The layer to be etched is then etched using the second hard mask layer pattern after the second photo resist pattern has been removed, resulting in patterns have line edges without rounding.Type: GrantFiled: May 3, 2001Date of Patent: May 27, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Soo Shin, Suk-Joo Lee, Jeung-Woo Lee, Dae-Youp Lee
-
Publication number: 20020059557Abstract: A method of forming fine patterns in a semiconductor device through a double photo lithography process. A layer to be etched and a hard mask layer are sequentially formed on a semiconductor substrate. A first photo resist pattern is formed on the hard mask layer. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After the first photo resist pattern is removed, a second photo resist pattern is formed on the resultant structure. A second hard mask layer pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. The layer to be etched is then etched using the second hard mask layer pattern after the second photo resist pattern has been removed, resulting in patterns have line edges without rounding.Type: ApplicationFiled: May 3, 2001Publication date: May 16, 2002Inventors: Hye-Soo Shin, Suk-Joo Lee, Jeung-Woo Lee, Dae-Youp Lee