Patents by Inventor Hye-Yeon Cheong

Hye-Yeon Cheong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230009225
    Abstract: A system comprises an encoder configured to compress media objects using a compression loop that includes a residual decomposition component that decomposes a residual signal for a block of the media object being compressed into multiple sub-error signals. The encoder is further configured to enable different transformation and/or quantization processes to be specified to be applied to different ones of the sub-errors. A corresponding decoder is configured to apply inverse transformation/quantization processing to the sub-error signals, based on the transformation/quantization processes that were applied at the encoder. The decoder then re-creates a residual signal from the processed sub-error signals and uses the re-created residual signal to correct predicted values at the decoder.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 12, 2023
    Inventors: Alexandros Tourapis, Hye-Yeon Cheong, David William Singer, Dominik Mehlem
  • Patent number: 11496770
    Abstract: A system includes an encoder configured to compress media objects using a compression loop that includes a residual decomposition component that decomposes a residual signal for a block of the media object being compressed into multiple sub-error signals. The encoder is further configured to enable different transformation and/or quantization processes to be specified to be applied to different ones of the sub-errors. A corresponding decoder is configured to apply inverse transformation/quantization processing to the sub-error signals, based on the transformation/quantization processes that were applied at the encoder. The decoder then re-creates a residual signal from the processed sub-error signals and uses the re-created residual signal to correct predicted values at the decoder.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 8, 2022
    Assignee: Apple Inc.
    Inventors: Alexandros Tourapis, Hye-Yeon Cheong, David William Singer, Dominik Mehlem
  • Publication number: 20220353543
    Abstract: A system comprises an encoder configured to compress video data using an in-loop noise generation process that generates noise in the compression loop at a sub-image portion level of granularity, such as at a block level. The encoder includes noise model and/or noise model input parameter information in an encoded bit stream. Also, a system includes a decoder configured to receive such a bit stream and decompress the video using an in-loop noise generation process that generates noise in the decompression loop at a sub-image portion level of granularity.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Hye-Yeon Cheong, David W. Singer, Alexandros Tourapis
  • Patent number: 11395008
    Abstract: A system comprises an encoder configured to compress video data using an in-loop noise generation process that generates noise in the compression loop at a sub-image portion level of granularity, such as at a block level. The encoder includes noise model and/or noise model input parameter information in an encoded bit stream. Also, a system includes a decoder configured to receive such a bit stream and decompress the video using an in-loop noise generation process that generates noise in the decompression loop at a sub-image portion level of granularity.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 19, 2022
    Assignee: Apple Inc.
    Inventors: Hye-Yeon Cheong, David W. Singer, Alexandros Tourapis
  • Patent number: 11265544
    Abstract: An image-processing apparatus to compress digital image data, includes a memory that stores a digital image in a first storage space. The image-processing apparatus further includes one or more image-processing circuits that selects a block from a plurality of blocks of the digital image. A plurality of encoded blocks is generated by application of a plurality of sequential encoding schemes on the selected block. One encoded block is detected from the generated plurality of encoded blocks that has a maximum bit-coverage value. A sequential encoding scheme is selected from the plurality of sequential encoding schemes as an optimal sequential encoding scheme. The selected sequential encoding scheme is associated with the detected encoded block with the maximum bit-coverage value. The selected block of the digital image is converted to a compressed bit stream storable in a reduced second storage space in the memory, by use of the sequential encoding scheme.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 1, 2022
    Assignee: SONY CORPORATION
    Inventors: Mohammed Golam Sarwer, Hye-Yeon Cheong, Ali Tabatabai
  • Publication number: 20210195246
    Abstract: A system comprises an encoder configured to compress media objects using a compression loop that includes a residual decomposition component that decomposes a residual signal for a block of the media object being compressed into multiple sub-error signals. The encoder is further configured to enable different transformation and/or quantization processes to be specified to be applied to different ones of the sub-errors. A corresponding decoder is configured to apply inverse transformation/quantization processing to the sub-error signals, based on the transformation/quantization processes that were applied at the encoder. The decoder then recreates a residual signal from the processed sub-error signals and uses the re-created residual signal to correct predicted values at the decoder.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 24, 2021
    Inventors: Alexandros Tourapis, Hye-Yeon Cheong, David William Singer, Dominik Mehlem
  • Publication number: 20210092459
    Abstract: A system comprises an encoder configured to compress video data using an in-loop noise generation process that generates noise in the compression loop at a sub-image portion level of granularity, such as at a block level. The encoder includes noise model and/or noise model input parameter information in an encoded bit stream. Also, a system includes a decoder configured to receive such a bit stream and decompress the video using an in-loop noise generation process that generates noise in the decompression loop at a sub-image portion level of granularity.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 25, 2021
    Inventors: Hye-Yeon Cheong, David W. Singer, Alexandros Tourapis
  • Patent number: 10931954
    Abstract: A media device includes a processor to calculate a value of an objective function for each sequence of modes of a plurality of sequences of modes, based on at least statistical data of a plurality of modes. The plurality of sequences of modes corresponds to different combinations of modes from the plurality of modes. The plurality of modes corresponds to a plurality of encoding operations executed. The processor selects a sequence of modes from the plurality of sequences of modes based on a value of the objective function associated with the sequence of modes. The modes in the selected sequence of modes are less than the plurality of modes and represents an optimal encoding scheme executable to encode an input image block.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: February 23, 2021
    Assignee: SONY CORPORATION
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Patent number: 10873747
    Abstract: To improve encoding efficiency, residual values are mapped so that only non-negative values are utilized when performing the encoding process.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: December 22, 2020
    Assignee: Sony Corporation
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Patent number: 10798419
    Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to determine a count of bits required to encode a plurality of quantized prediction residual levels in each sub-block of a plurality of sub-blocks of an image block, for a first coding scheme and a second coding scheme. The encoder circuitry allocates a bit value to a signaling bit for each sub-block of the plurality of sub-blocks, based on the determined count of bits. A value of the signaling bit represents either the first coding scheme or the second coding scheme. The encoder circuitry generates a bit-stream of the image block by selective application of either the first coding scheme or the second coding scheme on each sub-block of the plurality of sub-blocks, based on the value allocated to the signaling bit for each sub-block of the plurality of sub-blocks.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 6, 2020
    Assignee: SONY CORPORATION
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Patent number: 10778990
    Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to determine a refinement start position in a bit-plane of an encoded data block based on a random number. The refinement start position is a position in the bit-plane based on a value of the random number. The encoder circuitry determines a refinement order in the bit-plane for refining un-coded bits present in the bit-plane, based on the determined refinement start position and a refinement step size. The refinement order is a sequence of positions of the un-coded bits in the bit-plane that will be refined in that sequence. The encoder circuitry refines the un-coded bits by allocating a refinement bit at the refinement start position in the bit-plane and then followed by the allocation of subsequent refinement bits in the determined refinement order.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 15, 2020
    Assignee: SONY CORPORATION
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Patent number: 10750182
    Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to encode a plurality of sub-blocks of an image block by an entropy coding scheme to generate a plurality of encoded data blocks. Each encoded data block includes a first plurality of bit-planes and a second plurality of bit-planes. The first plurality of bit-planes include a plurality of entropy coded bits. The encoder circuitry determines a count of refinement bits of a plurality of refinement bits, for an encoded data block of the plurality of encoded data blocks, based on a quality measure of the plurality of encoded data blocks. The quality measure represents a count of the plurality of entropy coded bits in each encoded data block. The encoder circuitry allocates the count of refinement bits in the second plurality of bit-planes of the encoded data block.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 18, 2020
    Assignee: SONY CORPORATION
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Patent number: 10750175
    Abstract: An image-processing apparatus and method for quantization partitioning for enhanced image compression, includes storage of an input image in a first storage space having a first storage access bandwidth. The image-processing apparatus selects a plurality of QP values from a defined QP range for a first block of a plurality of blocks of the input image. The plurality of QP values are selected from the defined QP range based on defined criteria. The image-processing apparatus is configured to encode, by the selected plurality of QP values, the first block to generate an encoded bit stream of the first block. The encoded bit stream of the first block is storable in a reduced second storage space in the memory with a reduced second storage access bandwidth.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 18, 2020
    Assignee: SONY CORPORATION
    Inventors: Hye-Yeon Cheong, Mohammed Golam Sarwer, Ali Tabatabai
  • Patent number: 10666985
    Abstract: A sub-block entropy coding method more efficiently encodes content. Specifically, by selecting the most optimal tables for each sub-block, the number of bits utilizes is minimized. Furthermore, based on results, tables are able to be eliminated as options to further reduce the number of signaling bits.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: May 26, 2020
    Assignee: Sony Corporation
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Publication number: 20200162739
    Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to encode a plurality of sub-blocks of an image block by an entropy coding scheme to generate a plurality of encoded data blocks. Each encoded data block includes a first plurality of bit-planes and a second plurality of bit-planes. The first plurality of bit-planes include a plurality of entropy coded bits. The encoder circuitry determines a count of refinement bits of a plurality of refinement bits, for an encoded data block of the plurality of encoded data blocks, based on a quality measure of the plurality of encoded data blocks. The quality measure represents a count of the plurality of entropy coded bits in each encoded data block. The encoder circuitry allocates the count of refinement bits in the second plurality of bit-planes of the encoded data block.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 21, 2020
    Inventors: HYE-YEON CHEONG, ALI TABATABAI
  • Publication number: 20200162763
    Abstract: A sub-block entropy coding method more efficiently encodes content. Specifically, by selecting the most optimal tables for each sub-block, the number of bits utilizes is minimized. Furthermore, based on results, tables are able to be eliminated as options to further reduce the number of signaling bits.
    Type: Application
    Filed: November 18, 2018
    Publication date: May 21, 2020
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Publication number: 20200162734
    Abstract: To improve encoding efficiency, residual values are mapped so that only non-negative values are utilized when performing the encoding process.
    Type: Application
    Filed: November 18, 2018
    Publication date: May 21, 2020
    Inventors: Hye-Yeon Cheong, Ali Tabatabai
  • Publication number: 20200162758
    Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to determine a count of bits required to encode a plurality of quantized prediction residual levels in each sub-block of a plurality of sub-blocks of an image block, for a first coding scheme and a second coding scheme. The encoder circuitry allocates a bit value to a signaling bit for each sub-block of the plurality of sub-blocks, based on the determined count of bits. A value of the signaling bit represents either the first coding scheme or the second coding scheme. The encoder circuitry generates a bit-stream of the image block by selective application of either the first coding scheme or the second coding scheme on each sub-block of the plurality of sub-blocks, based on the value allocated to the signaling bit for each sub-block of the plurality of sub-blocks.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: HYE-YEON CHEONG, ALI TABATABAI
  • Publication number: 20200162746
    Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to determine a refinement start position in a bit-plane of an encoded data block based on a random number. The refinement start position is a position in the bit-plane based on a value of the random number. The encoder circuitry determines a refinement order in the bit-plane for refining un-coded bits present in the bit-plane, based on the determined refinement start position and a refinement step size. The refinement order is a sequence of positions of the un-coded bits in the bit-plane that will be refined in that sequence. The encoder circuitry refines the un-coded bits by allocating a refinement bit at the refinement start position in the bit-plane and then followed by the allocation of subsequent refinement bits in the determined refinement order.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: HYE-YEON CHEONG, ALI TABATABAI
  • Publication number: 20200162742
    Abstract: A media device includes a processor to calculate a value of an objective function for each sequence of modes of a plurality of sequences of modes, based on at least statistical data of a plurality of modes. The plurality of sequences of modes corresponds to different combinations of modes from the plurality of modes. The plurality of modes corresponds to a plurality of encoding operations executed. The processor selects a sequence of modes from the plurality of sequences of modes based on a value of the objective function associated with the sequence of modes. The modes in the selected sequence of modes are less than the plurality of modes and represents an optimal encoding scheme executable to encode an input image block.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 21, 2020
    Inventors: HYE-YEON CHEONG, ALI TABATABAI