Patents by Inventor Hye Yeon Ryu

Hye Yeon Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating nano-wire array
    Patent number: 7846786
    Abstract: Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other with the patterned nano-wires interposed therebetween; forming a plurality of drain electrodes which have one end connected to the drain electrode line and contact at least one of the nano-wires, and forming a plurality of source electrodes, which have one end connected to the source electrode line and contact the nano-wires that contact the drain electrodes; forming a second etch region between pairs of the drain and source electrodes so as to prevent electrical contacts between the pairs of the drain and source electrodes; forming an insulating layer on the substrate; and forming a gate electrode between the drain and source electrodes contacting the nano-wires on the insulating layer.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: December 7, 2010
    Assignees: Korea University Industrial & Academic Collaboration Foundation, Electronics and Telecommunications Research Institute
    Inventors: Hong Yeol Lee, Seung Eon Moon, Eun Kyoung Kim, Jong Hyurk Park, Kang Ho Park, Jong Dae Kim, Gyu Tae Kim, Jae Woo Lee, Hye Yeon Ryu, Jung Hwan Huh
  • METHOD OF FABRICATING NANO-WIRE ARRAY
    Publication number: 20080233675
    Abstract: Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other with the patterned nano-wires interposed therebetween; forming a plurality of drain electrodes which have one end connected to the drain electrode line and contact at least one of the nano-wires, and forming a plurality of source electrodes, which have one end connected to the source electrode line and contact the nano-wires that contact the drain electrodes; forming a second etch region between pairs of the drain and source electrodes so as to prevent electrical contacts between the pairs of the drain and source electrodes; forming an insulating layer on the substrate; and forming a gate electrode between the drain and source electrodes contacting the nano-wires on the insulating layer.
    Type: Application
    Filed: October 30, 2007
    Publication date: September 25, 2008
    Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATION
    Inventors: Hong Yeol Lee, Seung Eon Moon, Eun Kyoung Kim, Jong Hyurk Park, Kang Ho Park, Jong Dae Kim, Gyu Tae Kim, Jae Woo Lee, Hye Yeon Ryu, Jung Hwan Huh