Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: A display apparatus includes a base substrate, a light emitting structure disposed on the base substrate, and a thin film encapsulation layer disposed on the light emitting structure and including at least one inorganic layer and at least one organic layer. The at least one inorganic layer includes a high density layer having a density of greater than or equal to about 2.0 g/cm3 and a low density layer having a density of less than about 2.0 g/cm3. The high density layer and the low density layer are in contact with each other.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: Disclosed is a hot-stamping component, which includes a base steel plate; and a plated layer on the base steel plate and including a first layer, a second layer, and an intermetallic compound portion having an island shape in the second layer, wherein the first layer and the second layer are sequentially stacked, and an area fraction of the intermetallic compound portion with respect to the second layer is an amount of 20% to 60%.

Abstract: A coil member according to an embodiment comprises: a substrate having a top surface and a bottom surface opposite the top surface; a first coil electrode disposed on the top surface of the substrate and including a first pattern electrode; and a second coil electrode disposed on the bottom surface of the substrate and including a second pattern electrode. The first coil electrode includes: a first outermost pattern electrode; a first innermost pattern electrode; and a central pattern electrode between the first outermost pattern electrode and the first innermost pattern electrode, wherein the line width of at least one of the first outermost pattern electrode or the first innermost pattern electrode is greater than the line width of the central pattern electrode.

Abstract: A coil member according to an embodiment comprises: a substrate having a first surface and a second surface opposite to the first surface; a first circuit pattern disposed on the first surface; and a plurality of bridge portions protruding from an end of the substrate, wherein the bridge portions are integrally formed with the substrate, and a shield layer is disposed on the bridge portions.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a lower structure in which a cell region and a chip guard region are defined, wherein the cell region and the chip guard region are divided along a first direction; a first lower stack structure formed on the lower structure in the chip guard region, the first lower stack structure including a plurality of first lower material layers, the first lower stack structure including a first etch stop layer along an edge thereof; a first upper stack structure formed on the first lower stack structure in the chip guard region, the first upper stack structure including a plurality of first upper material layers; and a first slit penetrating the first upper stack structure to expose the first etch stop layer in the chip guard region.

Abstract: The present technology relates to a semiconductor memory device. The semiconductor memory device includes a plurality of channel plugs disposed in a cell region of a semiconductor substrate, a first dummy region and a second dummy region disposed at both end portions of the cell region, and first dummy plugs disposed in the first dummy region and second dummy plugs disposed in the second dummy region. A critical value of the first dummy plugs arranged in the first dummy region is different from a critical value of the second dummy plugs disposed in the second dummy region.

Abstract: A memory device, and a method of manufacturing the same, includes a source layer over which a cell region and a peripheral circuit region are defined, memory blocks formed on the source layer in the cell region, and a slit formed between the memory blocks. The memory device also includes a resistor formed in the source layer in the peripheral circuit region, contacts formed on the resistor, and metal lines formed on the contacts and connected to a peripheral circuit.

Abstract: A semiconductor memory device includes a discharge contact passing through a source structure, a gate stack disposed on a partial region of the source structure, a vertical structure passing through the gate stack, and an insulating pattern passing through the source structure between the vertical structure and the discharge contact.

Abstract: A coil member according to an embodiment comprises: a substrate having a top surface and a bottom surface opposite the top surface; a first coil electrode disposed on the top surface of the substrate and including a first pattern electrode; and a second coil electrode disposed on the bottom surface of the substrate and including a second pattern electrode. The first coil electrode includes: a first outermost pattern electrode; a first innermost pattern electrode; and a central pattern electrode between the first outermost pattern electrode and the first innermost pattern electrode, wherein the line width of at least one of the first outermost pattern electrode or the first innermost pattern electrode is greater than the line width of the central pattern electrode.

Abstract: A coil member according to an embodiment comprises: a substrate including an upper surface and a lower surface opposite to the upper surface; a first coil electrode disposed on the upper surface of the substrate and including first pattern electrodes; a second coil electrode disposed on the lower surface of the substrate and including second pattern electrodes; and third pattern electrodes disposed on the upper surface and the lower surface of the substrate, wherein a distance between the first pattern electrodes is different from a distance between the first pattern electrodes and the third pattern electrodes, and a distance between the second pattern electrodes is different from a distance between the second pattern electrodes and the third pattern electrodes.

Abstract: The present technology provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a cell source structure, a first stack disposed on the cell source structure and including insulating patterns and conductive patterns that are alternately stacked with each other, a peripheral source structure, and a resistor pattern disposed on the peripheral source structure. The resistor pattern is disposed at substantially the same level as a lowermost insulating pattern of the first stack.

Abstract: The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes an insulating film passing through a dummy source structure, a first dummy stack extending to overlap the insulating film and the dummy source structure, and including a depression overlapping the insulating film, a resistive film overlapping the depression of the first dummy stack, and a second dummy stack disposed on the first dummy stack to cover the resistive film.

Abstract: In a method of inspecting an error, a lower wiring structure may be formed. A main dummy pattern and a test dummy pattern may be formed on the lower wiring structure, The main dummy pattern may include a via pattern and a wiring pattern having a width greater than a width of the via pattern. The test dummy pattern may be spaced apart from the main dummy pattern by no less than a critical distance. The test dummy pattern may have a width substantially the same as that of the via pattern. The test dummy pattern may have a height substantially the same as that of the main dummy pattern. The test dummy pattern may then be tested to predict an error of the main dummy pattern based on an error of the test dummy pattern.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: A semiconductor device includes: a first stack structure with first insulating patterns and first conductive patterns, alternately stacked, the first stack structure with a first stepped structure that is defined by the first insulating patterns and the first conductive patterns; a second stack structure with second insulating patterns and second conductive patterns, alternately stacked on the first stack structure; and a first protrusion stack structure protruding laterally toward the first stepped structure from the second stack structure, the first protrusion stack structure with first protrusion insulating patterns and first protrusion conductive patterns, alternately stacked on the first stack structure. A sidewall of the first protrusion stack structure includes side surfaces of the first protrusion insulating patterns and side surfaces of the first protrusion conductive patterns, which form a common surface.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell source structure; a first stack structure disposed on the cell source structure; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a first peripheral transistor including impurity regions. A level of a bottom surface of each of the impurity regions is higher than that of a bottom surface of the cell source structure, and a level of a top surface of each of the impurity regions is lower than that of a top surface of the cell source structure.

Abstract: The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes an insulating film passing through a dummy source structure, a first dummy stack extending to overlap the insulating film and the dummy source structure, and including a depression overlapping the insulating film, a resistive film overlapping the depression of the first dummy stack, and a second dummy stack disposed on the first dummy stack to cover the resistive film.