Abstract: A semiconductor device includes an active region, a gate dielectric layer disposed on the active region, a gate electrode disposed on the gate dielectric layer, a protective layer in contact with a portion of a side surface of the gate electrode, and a spacer structure covering the side surface of the gate electrode and the protective layer. The gate electrode includes a lower conductive pattern disposed on the gate dielectric layer, an intermediate conductive pattern disposed on the lower conductive pattern, and an upper conductive pattern disposed on the intermediate conductive pattern. The protective layer includes a first protective portion in contact with at least a portion of a side surface of the intermediate conductive pattern and a second protective portion in contact with a side surface of the upper conductive pattern, and the second protective portion includes a material different from a material of the first protective portion.

Abstract: A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.

Abstract: A method of manufacturing a semiconductor device including partially etching an upper portion of a substrate to form a recess extending in a first direction parallel to an upper surface of the substrate, forming a gate structure in the recess, the gate structure including a first conductive pattern, a second conductive pattern on the first conductive pattern, and a gate mask on the second conductive pattern, partially etching an end portion of the gate structure in the first direction to form an opening, the opening extending through end portions of the gate mask and the second conductive pattern of the gate structure to expose a portion of the first conductive pattern, and a bottom of the opening being lower than a lower surface of the exposed portion of the first conductive pattern, and forming a contact plug in the opening.

Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.

Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.

Abstract: A semiconductor device includes a substrate having first and second active patterns therein, which are spaced apart from each other. The first active pattern has a top surface that is elevated relative to a top surface of the second active pattern. A channel semiconductor layer is provided on the top surface of the first active pattern. A first gate pattern is provided, which includes a first insulating pattern, on the channel semiconductor layer. A second gate pattern is provided, which includes a second insulating pattern having a thickness greater than a thickness of the first insulating pattern, on the top surface of the second active pattern.

Abstract: A semiconductor device includes an active region, a gate dielectric layer disposed on the active region, a gate electrode disposed on the gate dielectric layer, a protective layer in contact with a portion of a side surface of the gate electrode, and a spacer structure covering the side surface of the gate electrode and the protective layer. The gate electrode includes a lower conductive pattern disposed on the gate dielectric layer, an intermediate conductive pattern disposed on the lower conductive pattern, and an upper conductive pattern disposed on the intermediate conductive pattern. The protective layer includes a first protective portion in contact with at least a portion of a side surface of the intermediate conductive pattern and a second protective portion in contact with a side surface of the upper conductive pattern, and the second protective portion includes a material different from a material of the first protective portion.

Abstract: A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.

Abstract: The present invention relates to a marker composition for diagnosing major depressive disorder, comprising ZA2G and prothrombin as markers, a method for providing information necessary to determine the occurrence of major depressive disorder using the marker composition, a composition for determining the occurrence of major depressive disorder, comprising agents for measurement of the expression levels of the markers, and a kit for determining the occurrence of major depressive disorder, comprising devices for measurement of the expression levels of the markers.

Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.