Patents by Inventor Hye Ji KIM

Hye Ji KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140161
    Abstract: A processor including: an interface circuit to receive first image data and convert the first image data into second image data; a pattern detecting circuit to detect a pattern in the first or second image data; a brightness detecting circuit to detect a panel brightness value, and to detect a ratio of pixels emitting light; and a real-time sensing circuit, wherein when the pattern is not detected, the real-time sensing circuit performs/stops real-time sensing of the pixels based on whether the panel brightness value is within a range and the ratio of pixels emitting light is greater than or equal to a first threshold; and when the pattern is detected, the real-time sensing circuit performs/stops the real-time sensing of the pixels based on whether the panel brightness value is within the range and the ratio of pixels emitting light is greater than or equal to a second threshold.
    Type: Application
    Filed: May 20, 2024
    Publication date: May 1, 2025
    Inventors: Ji Woong JEONG, Hye Ji KIM, Jung Ki MIN, Bo Young AN
  • Publication number: 20240362297
    Abstract: Disclosed herein are an outer product-based matrix-vector multiplication operation apparatus and a method using the same. The outer product-based matrix-vector multiplication operation apparatus includes internal calculators, each configured to generate an accumulated value by performing a Multiply-Accumulation (MAC) operation, an internal data transmission path configured to simultaneously provide a vector element to two or more internal calculators, and at least one multiplexer configured to select any one of the vector element and a vector of a matrix, wherein a first input port of each of the internal calculators is connected to one of vectors of the matrix and a second input port of each of the internal calculators is connected to the vector element.
    Type: Application
    Filed: November 6, 2023
    Publication date: October 31, 2024
    Inventor: Hye-Ji KIM
  • Publication number: 20240150681
    Abstract: The present disclosure relates to a cleaning agent composition for a substrate for a semiconductor device and a method for cleaning a substrate for a semiconductor device using the same. The cleaning agent composition contains a silicon-based compound represented by Formula 1 and an aprotic organic solvent with a dielectric constant of 10 or less, which can form a surface protective film capable of preventing collapse of the pattern even in a wet cleaning process of fine patterns with high aspect ratios, thereby providing a method for manufacturing a semiconductor device with an improved semiconductor manufacturing yield.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 9, 2024
    Inventors: Hye Ji KIM, JinHo YOU, Hag Sung LEE, MyungHo LEE, Narae YIM, Yu jin HEO, Keon young KIM, Yun sun CHOI, Young mee KANG
  • Publication number: 20240148856
    Abstract: Provided is a vaccine composition for preventing respiratory syncytial virus (RSV) infection, which is in the form of a liposome formulation including a RSV antigen, monophosphoryl lipid A (MLA), and/or a cobalt-porphyrin-phospholipid (CoPoP) conjugate. The vaccine composition exhibits excellent vaccine efficacy from a RSV antigen with enhanced immunogenicity and a combination of immune adjuvants for enhancing immune activity and antigen presentation.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 9, 2024
    Applicant: EUBIOLOGICS CO., LTD.
    Inventors: Chan Kyu LEE, Jonathan F. LOVELL, Yoon Hee WHANG, Woo Yeon HWANG, Hye Ji KIM, Min Chul PARK, Seok Kyu KIM, Wei-Chiao HUANG, Da Hui HA
  • Publication number: 20240062809
    Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho HAN, Byung-Jo KIM, Ju-Yeob KIM, Hye-Ji KIM, Joo-Hyun LEE, Seong-Min KIM
  • Patent number: 11842764
    Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: December 12, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho Han, Byung-Jo Kim, Ju-Yeob Kim, Hye-Ji Kim, Joo-Hyun Lee, Seong-Min Kim
  • Publication number: 20230367553
    Abstract: Disclosed herein are an apparatus and method for a multiplication operation based on an outer product. The apparatus may include first internal calculators, each of which generates an intermediate accumulation value by performing a Multiply-Accumulate (MAC) operation, second internal calculators, each of which generates a chunking accumulation value using the intermediate accumulation value, and accumulation data transmission paths for enabling the output of any one of the first internal calculators to be input to any one of the second internal calculators.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 16, 2023
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Hye-Ji KIM
  • Patent number: 11735092
    Abstract: A display device includes first pixels partitioned into a plurality of blocks, each of the plurality of blocks being categorized as a first block or a second block, a sensor configured to generate first sensing data for at least two of the first pixels in each of the plurality of blocks during a first period, and a sensing controller configured to generate interpolated data for the first pixels that are not sensed by the sensor by interpolating the first sensing data, for the first block, and configured to forgo interpolation of the first sensing data, for the second block. The sensor generates second sensing data for the first pixels that are not sensed by the sensor, for the second block, during a second period after the first period.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: August 22, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su Min Yang, Wook Lee, Hye Ji Kim, Ki Hyun Pyun
  • Publication number: 20230259581
    Abstract: Disclosed herein is a method for outer-product-based matrix multiplication for a floating-point data type includes receiving first floating-point data and second floating-point data and performing matrix multiplication on the first floating-point data and the second floating-point data, and the result value of the matrix multiplication is calculated based on the suboperation result values of floating-point units.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 17, 2023
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Won JEON, Young-Su KWON, Ju-Yeob KIM, Hyun-Mi KIM, Hye-Ji KIM, Chun-Gi LYUH, Mi-Young LEE, Jae-Hoon CHUNG, Yong-Cheol CHO, Jin-Ho HAN
  • Publication number: 20230197474
    Abstract: The present disclosure provides a heating unit capable of using a bush with holes and a substrate treating apparatus including the same. An apparatus for treating a substrate, includes a heating unit including a heating plate and configured to heat the substrate, a cooling unit configured to cool the substrate, and a transfer unit configured to move the substrate to the heating unit or the cooling unit, wherein the heating plate includes a first plate configured to provide a seating surface to the substrate, and a second plate disposed under the first plate and installed internally with heater(s) and bush(es), and wherein the bush has a hollow configured to provide a lift pin with a space of movement for allowing the lift pin to be elevated or lowered, and includes a plurality of holes formed to extend from the hollow in an outward direction.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 22, 2023
    Inventors: Dong Min CHOI, Hye Ji KIM
  • Publication number: 20230017238
    Abstract: The present invention relates to a stripper composition for removing a photoresist in a process of manufacturing a semiconductor device. According to the present invention, it is possible to prevent corrosion of the underlying film while improving the peeling force for the photoresist, and to improve the stability of the composition over time.
    Type: Application
    Filed: June 20, 2022
    Publication date: January 19, 2023
    Inventors: Hye Ji KIM, Jin Ho YOU, Namgi CHO
  • Patent number: 11542577
    Abstract: A magnesium alloy sheet according to an embodiment of the present invention includes greater than 3 wt % and less than or equal to 5 wt % of Al, 0.5 wt % to 1.5 wt % of Zn, 0.1 wt % to 0.5 wt % of Mn, 0.001 wt % to 0.01 wt % of B, 0.1 wt % to 0.5 wt % of Y, a balance amount of magnesium, and other inevitable impurities on the basis of a total of 100 wt %.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: January 3, 2023
    Assignee: POSCO HOLDINGS INC.
    Inventors: Jae Sin Park, Taek Geun Lee, Dae Hwan Choi, Bae Mun Seo, Hye Ji Kim, Jonggeol Kim, Hye Jeong Kim, Yoonsuk Oh, Jae Eock Cho, Dong Kyun Choo
  • Publication number: 20220215789
    Abstract: A display device includes first pixels partitioned into a plurality of blocks, each of the plurality of blocks being categorized as a first block or a second block, a sensor configured to generate first sensing data for at least two of the first pixels in each of the plurality of blocks during a first period, and a sensing controller configured to generate interpolated data for the first pixels that are not sensed by the sensor by interpolating the first sensing data, for the first block, and configured to forgo interpolation of the first sensing data, for the second block. The sensor generates second sensing data for the first pixels that are not sensed by the sensor, for the second block, during a second period after the first period.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Inventors: Su Min YANG, Wook LEE, Hye Ji KIM, Ki Hyun PYUN
  • Publication number: 20220180919
    Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 9, 2022
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin-Ho HAN, Byung-Jo KIM, Ju-Yeob KIM, Hye-Ji KIM, Joo-Hyun LEE, Seong-Min KIM
  • Patent number: 11282433
    Abstract: A display device includes first pixels partitioned into a plurality of blocks, each of the plurality of blocks being categorized as a first block or a second block, a sensor configured to generate first sensing data for at least two of the first pixels in each of the plurality of blocks during a first period, and a sensing controller configured to generate interpolated data for the first pixels that are not sensed by the sensor by interpolating the first sensing data, for the first block, and configured to forgo interpolation of the first sensing data, for the second block. The sensor generates second sensing data for the first pixels that are not sensed by the sensor, for the second block, during a second period after the first period.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 22, 2022
    Inventors: Su Min Yang, Wook Lee, Hye Ji Kim, Ki Hyun Pyun
  • Publication number: 20210150966
    Abstract: A display device includes first pixels partitioned into a plurality of blocks, each of the plurality of blocks being categorized as a first block or a second block, a sensor configured to generate first sensing data for at least two of the first pixels in each of the plurality of blocks during a first period, and a sensing controller configured to generate interpolated data for the first pixels that are not sensed by the sensor by interpolating the first sensing data, for the first block, and configured to forgo interpolation of the first sensing data, for the second block. The sensor generates second sensing data for the first pixels that are not sensed by the sensor, for the second block, during a second period after the first period.
    Type: Application
    Filed: August 5, 2020
    Publication date: May 20, 2021
    Inventors: Su Min YANG, Wook LEE, Hye Ji KIM, Ki Hyun PYUN
  • Publication number: 20210140017
    Abstract: A magnesium alloy sheet according to an embodiment of the present invention includes greater than 3 wt % and less than or equal to 5 wt % of Al, 0.5 wt % to 1.5 wt % of Zn, 0.1 wt % to 0.5 wt % of Mn, 0.001 wt % to 0.01 wt % of B, 0.1 wt % to 0.5 wt % of Y, a balance amount of magnesium, and other inevitable impurities on the basis of a total of 100 wt %.
    Type: Application
    Filed: December 3, 2018
    Publication date: May 13, 2021
    Inventors: Jae Sin Park, Taek Geun Lee, Dae Hwan Choi, Bae Mun Seo, Hye Ji Kim, Jonggeol Kim, Hye Jeong Kim, Yoonsuk Oh, Jae Eock Cho, Dong Kyun Choo
  • Patent number: 10067821
    Abstract: An apparatus and method for cyclic redundancy check device is provided. The apparatus includes a multiplicity of sub-block CRC parts configured to receive a bit sequence from each sub-block of a transport block that is divided into a multiplicity of sub-blocks and to perform CRC, and a Galois field adding part configured to add second codes, which are output from the multiplicity of sub-block CRC parts, in a Galois field, wherein each sub-block CRC part includes a Galois field multiplying part configured to generate a weight bit sequence by multiplying a first code, which is obtained from CRC calculation of a sub-block weight code that represents a weight allocated to each sub-block, and the bit sequence in the Galois field, and a linear feedback shift register including n-numbered registers and configured to output the second code by adding the weight bit sequence to each register in the Galois field.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 4, 2018
    Assignee: CENTER FOR INTEGRATED SMART SENSORS FOUNDATION
    Inventors: Hye Ji Kim, Ji Hoon Kim
  • Patent number: 9613821
    Abstract: Provided are a method of forming patterns and a method of manufacturing an integrated circuit device. In the method of forming patterns, a photoresist pattern having a first opening exposing a first region of a target layer is formed. A capping layer is formed at sidewalls of the photoresist pattern defining the first opening. An insoluble region is formed around the first opening by diffusing acid from the capping layer to the inside of the photoresist pattern. A second opening exposing a second region of the target layer is formed by removing a soluble region spaced apart from the first opening, with the insoluble region being interposed therebetween. The target layer is etched using the insoluble region as an etch mask.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yool Kang, Dong-won Kim, Ju-young Kim, Tae-hoon Kim, Hye-ji Kim, Su-min Park, Hyung-rae Lee
  • Publication number: 20160371142
    Abstract: An apparatus and method for cyclic redundancy check device is provided. The apparatus includes a multiplicity of sub-block CRC parts configured to receive a bit sequence from each sub-block of a transport block that is divided into a multiplicity of sub-blocks and to perform CRC, and a Galois field adding part configured to add second codes, which are output from the multiplicity of sub-block CRC parts, in a Galois field, wherein each sub-block CRC part includes a Galois field multiplying part configured to generate a weight bit sequence by multiplying a first code, which is obtained from CRC calculation of a sub-block weight code that represents a weight allocated to each sub-block, and the bit sequence in the Galois field, and a linear feedback shift register including n-numbered registers and configured to output the second code by adding the weight bit sequence to each register in the Galois field.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 22, 2016
    Inventors: Hye Ji KIM, Ji Hoon KIM