Abstract: An apparatus for non-invasively measuring bio-information is provided. The apparatus for estimating bio-information may include a pulse wave sensor configured to measure a pulse wave signal from an object; a sensor position sensor configured to obtain sensor position information of the pulse wave sensor with respect to the object, based on the object being in contact with the pulse wave sensor; and a processor configured to estimate the bio-information based on blood vessel position information of the object, the sensor position information, and the pulse wave signal.

Abstract: In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.

Abstract: In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.