Abstract: A mode-detecting device is described which comprises a first and a second synchronization detecting unit which receive a vertical synchronization signal and a horizontal synchronization signal. A vertical synchronization delay unit delays the Vp section of the vertical synchronization signal by 24H of the horizontal synchronization signal. A pulse generating unit generates a pulse from the 600th clock of the clock signals of the delayed vertical synchronization signal. First and a second detecting units receive the pulse from the 600th clock as a clock input and respectively receive the vertical and horizontal synchronization signals. Upon detecting the 600th clock, the polarity of the vertical and the horizontal synchronization signals are respectively output to first and second selecting means, and can be used to determine one of a plurality of display modes so that automatic centering can be accomplished.

Abstract: A circuit for outputting a liquid crystal display controlling signal in inputting a data enable signal. A circuit for controlling an LCD drive integrated circuit by a horizontal synchronous signal and a circuit for controlling the LCD drive IC by the data enable signal are separately designed in a conventional circuit for outputting the LCD-controlling signal. However, conventionally, the number of both pins and gates of the application specific integrated circuit which makes up the conventional circuit are increased. The present circuit uses data enable and HSYNC signals through one pin, makes the HSYNC signal by using the data enable signal, and instead of a circuit for controlling the LCD drive IC by the data enable signal, it uses a circuit for controlling the LCD drive IC by the HSYNC signal, thereby reducing the number of gates and optimizing the circuit.