Abstract: A display driving device including: a gate driver configured to provide a first gate selection signal to a first gate line of a display panel to select the first gate line; a source driver configured to provide an image signal corresponding to the first gate line to a source line; an Electrostatic Discharge (ESD) detection circuit configured to receive a power supply voltage, determine whether there is an ESD in the power supply voltage and, when the ESD is detected, generate a first detection signal; and a controller configured to receive the first detection signal to generate a masking signal, wherein the gate driver is configured to receive the masking signal and not provide a second gate selection signal to select a second gate line.

Abstract: A source driver for a display device includes a gamma voltage generation circuit, first through (2m)-th data driving circuits, and a switch circuit. The gamma voltage generation circuit generates R, G and B gamma voltages. The (2k?1)-th data driving circuits consecutively receive red image data and blue image data, and consecutively generate a R driving voltage and a B driving voltage using the R gamma voltages and B gamma voltages, respectively, during one horizontal period. The (2k)-th data driving circuits consecutively receive first green image data and second green image data, and consecutively generate a G1 driving voltage and a G2 driving voltage, respectively, using the G gamma voltages during the one horizontal period. The switch circuit outputs the R, B, G1, and G2 driving voltages through different data lines from each other based on a first selection signal and a second selection signal.

Abstract: A source driver for a display device includes a gamma voltage generation circuit, first through (2m)-th data driving circuits, and a switch circuit. The gamma voltage generation circuit generates R, G and B gamma voltages. The (2k?1)-th data driving circuits consecutively receive red image data and blue image data, and consecutively generate a R driving voltage and a B driving voltage using the R gamma voltages and B gamma voltages, respectively, during one horizontal period. The (2k)-th data driving circuits consecutively receive first green image data and second green image data, and consecutively generate a G1 driving voltage and a G2 driving voltage, respectively, using the G gamma voltages during the one horizontal period. The switch circuit outputs the R, B, G1, and G2 driving voltages through different data lines from each other based on a first selection signal and a second selection signal.

Abstract: A source driver for a display device includes a gamma voltage generation circuit, first through (2m)-th data driving circuits, and a switch circuit. The gamma voltage generation circuit generates R, G and B gamma voltages. The (2k?1)-th data driving circuits consecutively receive red image data and blue image data, and consecutively generate a R driving voltage and a B driving voltage using the R gamma voltages and B gamma voltages, respectively, during one horizontal period. The (2k)-th data driving circuits consecutively receive first green image data and second green image data, and consecutively generate a G1 driving voltage and a G2 driving voltage, respectively, using the G gamma voltages during the one horizontal period. The switch circuit outputs the R, B, G1, and G2 driving voltages through different data lines from each other based on a first selection signal and a second selection signal.

Abstract: A source driver for a display device includes a gamma voltage generation circuit, first through (2m)-th data driving circuits, and a switch circuit. The gamma voltage generation circuit generates R, G and B gamma voltages. The (2k?1)-th data driving circuits consecutively receive red image data and blue image data, and consecutively generate a R driving voltage and a B driving voltage using the R gamma voltages and B gamma voltages, respectively, during one horizontal period. The (2k)-th data driving circuits consecutively receive first green image data and second green image data, and consecutively generate a G1 driving voltage and a G2 driving voltage, respectively, using the G gamma voltages during the one horizontal period. The switch circuit outputs the R, B, G1, and G2 driving voltages through different data lines from each other based on a first selection signal and a second selection signal.

Abstract: A DC-DC converter includes a charge pump unit and a clock pulse generator unit. The charge pump unit precharges a boost node in response to a precharge clock pulse and boosts the boost node to a boosted voltage in response to a pump clock pulse. The clock pulse generator unit generates the precharge clock pulse and the pump clock pulse in which corresponding pulse widths increase during multiple time intervals over time.

Abstract: A multi-display (e.g., dual-display) driving circuit includes a first display driving circuit configured to receive a first display signal and a second display signal from an external source (e.g., CPU) through a first interface, and to drive a first display panel in response to the first display signal and to output the second display signal through a second interface of the first display driving circuit. The second display signal is transmitted via the second interface to a second driving circuit configured to drive a second display panel. Therefore, the complexity of the wiring (e.g., through a hinge of a folding phone, and between a CPU and first and second displays) of the multi-display device may be reduced, and the electromagnetic interference (EMI) characteristics of the multi-display device may be enhanced.

Abstract: A DC-DC converter includes a charge pump unit and a clock pulse generator unit. The charge pump unit precharges a boost node in response to a precharge clock pulse and boosts the boost node to a boosted voltage in response to a pump clock pulse. The clock pulse generator unit generates the precharge clock pulse and the pump clock pulse in which corresponding pulse widths increase during multiple time intervals over time.

Abstract: A source driver circuit in which a slow rate is adjusted according to a frame frequency and a method for adjusting a slew rate according to a frame frequency in the source driver circuit, wherein the source driver circuit includes a plurality of driver amplifiers, a frequency-current converting unit, and a bias current outputting unit. The driver amplifiers receive input voltages, generate output voltages, and adjust slew rates of the output voltages according to an amount of a bias current. The frequency-current converting unit receives a frame frequency and outputs a control current having an amount of the control current adjusted according to the frame frequency. The bias current outputting unit adjusts an amount of a bias current according to the amount of the control current and outputs the adjusted bias current to the driver amplifiers.

Abstract: A multi-display (e.g., dual-display) driving circuit includes a first display driving circuit configured to receive a first display signal and a second display signal from an external source (e.g., CPU) through a first interface, and to drive a first display panel in response to the first display signal and to output the second display signal through a second interface of the first display driving circuit. The second display signal is transmitted via the second interface to a second driving circuit configured to drive a second display panel. Therefore, the complexity of the wiring (e.g., through a hinge of a folding phone, and between a CPU and first and second displays) of the multi-display device may be reduced, and the electromagnetic interference (EMI) characteristics of the multi-display device may be enhanced.

Abstract: Provided are a phase locked loop (PLL) circuit having a wide locked range and a semiconductor integrated circuit (IC) device having the PLL circuit.

Abstract: Provided are a phase locked loop (PLL) circuit having a wide locked range and a semiconductor integrated circuit (IC) device having the PLL circuit.

Abstract: A CRT driving voltage generating apparatus which can be realized and integrated at low cost, and can prevent breakdown and malfunction of circuits by actively adapting to a change in the frequency of a horizontal synchronous signal, and a CRT driving voltage generating method performed by the apparatus are provided. In this apparatus, a first comparator compares a reference value with the peak value of a fly back pulse. A stability controller shifts the level of the result of the comparison using a current mirroring technique and outputs a compared signal having a shifted level. A second comparator compares the compared signal with a sensing signal to obtain a reset signal. A pulse width modulated signal generator outputs a pulse width modulated signal having a level which is determined in response to the logic levels of a clock signal and a reset signal. A driving voltage generator generates the CRT driving voltage in response to the pulse width modulated signal.

Abstract: A brightness correcting circuit and method for efficiently correcting the brightness of the edges and the corners of a monitor screen are provided. The circuit for correcting the brightness of the monitor screen which operates according to the brightness correcting method includes a parabolic signal generator for generating a parabolic signal and a corrected video signal generator for controlling the gain of an input video signal in response to the parabolic signal and outputting a corrected video signal.

Abstract: There is provided a correlative double sampling (CDS) device which can effectively and efficiently remove noise from video signal. The CDS device includes at least two sample-and-hold circuits for sampling a video signal output from an image sensor and outputting a predetermined DC level signal, and a differential amplifier. The correlative double sampling device also includes a clamping circuit for DC-clamping a video signal output from the image sensor and applying the DC-clamped signal to the sample-and-hold circuits. At least two re-sample-and-hold circuits are provided for re-sampling the signal output from the sample-and-hold circuits. A level correcting portion is used for correcting the output level of one of the sample-and-hold circuits and one of the re-sample-and-hold circuits, and outputting a signal whose phase is synchronized with the output of the re-sample-and-hold circuits.