Patents by Inventor Hyeok Jun Choe
Hyeok Jun Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768618Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: GrantFiled: September 7, 2021Date of Patent: September 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Cho, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Patent number: 11360666Abstract: A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.Type: GrantFiled: April 29, 2020Date of Patent: June 14, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Hyun Hong, Young Jin Cho, Hyeok Jun Choe, Young Geon Yoo, Chan Ho Yoon
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Publication number: 20220147458Abstract: A semiconductor device includes a device memory, and a device coherency engine (DCOH) that shares a coherency state of the device memory based on data in a host device and a host memory. A power supply of device memory is dynamically adjusted based on the coherency state.Type: ApplicationFiled: August 4, 2021Publication date: May 12, 2022Inventors: JEONG HO LEE, DAE HUI KIM, YOUN HO JEON, HYEOK JUN CHOE
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Publication number: 20220100669Abstract: A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.Type: ApplicationFiled: August 16, 2021Publication date: March 31, 2022Inventors: Hyeok Jun Choe, Youn Ho Jeon, Young Geon Yoo, Hyo-Deok Shin, I Poom Jeong
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Publication number: 20210405875Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: ApplicationFiled: September 7, 2021Publication date: December 30, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Cho, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Patent number: 11137921Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: GrantFiled: September 4, 2019Date of Patent: October 5, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Cho, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Publication number: 20210109655Abstract: A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.Type: ApplicationFiled: April 29, 2020Publication date: April 15, 2021Inventors: JUNG HYUN HONG, YOUNG JIN CHO, HYEOK JUN CHOE, YOUNG GEON YOO, CHAN HO YOON
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Publication number: 20200285392Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: ApplicationFiled: September 4, 2019Publication date: September 10, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin CHO, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Patent number: 10509744Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.Type: GrantFiled: December 15, 2017Date of Patent: December 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong Ho Lee, Sung Roh Yoon, Eui Young Chung, Jin Woo Kim, Young Jin Cho, Myeong Jin Kim, Sei Joon Kim, Jeong Bin Kim, Hyeok Jun Choe
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Publication number: 20180189206Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.Type: ApplicationFiled: December 15, 2017Publication date: July 5, 2018Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: JEONG HO LEE, SUNG ROH YOON, EUI YOUNG CHUNG, JIN WOO KIM, YOUNG JIN CHO, MYEONG JIN KIM, SEI JOON KIM, JEONG BIN KIM, HYEOK JUN CHOE
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Patent number: 9529100Abstract: The present disclosure relates to a positron emission tomography detector and a positron emission tomography system using the same. More particularly, the positron emission tomography detector includes: a lower detecting unit configured to have a plurality of detector modules disposed in a ring or polygonal shape; and an upper detecting unit configured to have a plurality of detector modules which are spaced apart from each other by a predetermined distance, or of which at least some are in contact with each other to be formed on the lower detecting unit, and formed in a conical shape which is tilted by a preset angle. By the configuration as described above, since the positron emission tomography detector and the positron emission tomography system using the same according to the present disclosure have a large number of effective lines of response (LOR) and increase geometric efficiency, it is possible to improve sensitivity.Type: GrantFiled: December 31, 2013Date of Patent: December 27, 2016Assignee: Sogang University Research FoundationInventors: Yong Choi, Hyeok Jun Choe
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Publication number: 20150378035Abstract: The present disclosure relates to a positron emission tomography detector and a positron emission tomography system using the same. More particularly, the positron emission tomography detector includes: a lower detecting unit configured to have a plurality of detector modules disposed in a ring or polygonal shape; and an upper detecting unit configured to have a plurality of detector modules which are spaced apart from each other by a predetermined distance, or of which at least some are in contact with each other to be formed on the lower detecting unit, and formed in a conical shape which is tilted by a preset angle. By the configuration as described above, since the positron emission tomography detector and the positron emission tomography system using the same according to the present disclosure have a large number of effective lines of response (LOR) and increase geometric efficiency, it is possible to improve sensitivity.Type: ApplicationFiled: December 31, 2013Publication date: December 31, 2015Applicant: Sogang University Research FoundationInventors: Yong Choi, Hyeok Jun Choe