Abstract: Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2n channels, where n is a natural number greater than 0, allocating a first channel of the 2n channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2 channels, where n is a natural number greater than 0, allocating a first channel of the 2 channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.

Abstract: Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: Provided is an apparatus and method for filtering a blocking effect in an image, which removes the blocking effect that may occur in an image that is compressed in block units in compression and/or decompression of a moving image. The apparatus and method for filtering a blocking effect in an image involves a single blocky pattern and a double blocky pattern and uses filtering that is suitable for these patterns. Also, the method for filtering a blocking effect in an image separately filters pixels in a top field and pixels in a bottom field when a macroblock in a frame picture is coded in a field mode.

Abstract: Two temporary buffers are employed alternatively storing a fail address data designated from a test operation, in which one of the temporary buffers transfers the fail address data to a data buffer in order to perform a repair analysis while the other one is storing the fail address data. Accordingly, the test and repair analysis operations are simultaneously performed. The capability of the rearrangement that includes the movement and exchange between the column and row fail address data enhances redundancy efficiency and yields of the memory device.

Abstract: Two temporary buffers are employed alternatively storing a fail address data designated from a test operation, in which one of the temporary buffers transfers the fail address data to a data buffer in order to perform a repair analysis while the other one is storing the fail address data. Accordingly, the test and repair analysis operations are simultaneously performed. The capability of the rearrangement that includes the movement and exchange between the column and row fail address data enhances redundancy efficiency and yields of the memory device.