Abstract: A water-cooled heat dissipation module assembly capable of cooling a power module of a vehicle driving inverter system using a battery or fuel cell. The water-cooled heat dissipation module assembly includes a housing unit provided in the form of a housing having an opening portion at least partially opened at one side thereof. The housing unit and at least a part of a rim region of the cooling unit are made of a plastic material, and the housing unit and the cooling unit are joined to each other by plastic welding using a laser.

Abstract: A battery device receives a state of charge (SOC) a SOC setting range, charge at least one battery pack, estimates a SOC based on state information of the at least one battery pack, monitors whether the estimated SOC reaches a charging reference value corresponding to an upper limit of the SOC setting range, and stops charging when it is confirmed through a result of the monitoring that the estimated SOC reaches the charging reference value. The SOC setting range may be determined based on driving information of a vehicle, and may be within a SOC limiting range in which degradation of battery cells included in the at least one battery pack is the lowest.

Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.

Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked; a field oxide film for separating the second semiconductor layer into a first region and a second region; a recess region formed in a particular region of the second region; gate insulating films and gate electrodes formed in stacks on each of a particular region in the first region and the recess region in the second region; first impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the first region; and second impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the recess region in the second region so that the second semiconductor layer below the gate electrode is fully depleted.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked; a field oxide film for separating the second semiconductor layer into a first region and a second region; a recess region formed in a particular region of the second region; gate insulating films and gate electrodes formed in stacks on each of a particular region in the first region and the recess region in the second region; first impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the first region; and second impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the recess region in the second region so that the second semiconductor layer below the gate electrode is fully depleted.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked; a field oxide film for separating the second semiconductor layer into a first region and a second region; a recess region formed in a particular region of the second region; gate insulating films and gate electrodes formed in stacks on each of a particular region in the first region and the recess region in the second region; first impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the first region; and second impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the recess region in the second region so that the second semiconductor layer below the gate electrode is fully depleted.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: Electrostatic discharge protection device is provided that protects the gate insulating layer without using an additional circuit to lower the trigger voltage of a thyristor. The electrostatic discharge protection device includes first and second impurity regions of a bipolar transistor being spaced a predetermined distance apart in a first conductivity type semiconductor substrate, and first and second impurity regions of a field transistor perpendicular to and along both sides of the first and second impurity regions of the bipolar transistor. A gate line formed between the first and second impurity regions of the bipolar transistor on the semiconductor substrate is coupled to one of the impurity regions of the field transistor. A Vss line is coupled to the other impurity region of the field transistor. The Vss line is also coupled to the first impurity region of the bipolar transistor. A metal layer is coupled to the first impurity region of the bipolar transistor and a pad.