Patents by Inventor Hyeokjin LIM
Hyeokjin LIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240076823Abstract: Disclosed herein is a washing machine and a control method thereof, and more particularly, to a technology capable of controlling washing modes in various manners by manipulating a control panel of the washing machine. The washing machine includes a display configured to display a washing mode, an inputter configured to receive a washing mode select command, a storage configured to store a selected washing mode, and a controller configured to allow a washing mode, which has the largest number of times selected during a predetermined number of times of washings, to be displayed on a first screen of the display, and in response to the number of the washing mode having the largest number of selection times being plural, configured to allow a washing mode, which is the last selected among the plurality of washing modes, to be displayed on the first screen of the display.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bobin KIM, Haeyoon PARK, Hansaem KIM, Joonho LEE, Kyoungae LIM, Dongmin LEE, Hyeokjin CHOI, Romon SON
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Patent number: 11710733Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2?m<PPG and PPG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch PPG>m*P.Type: GrantFiled: March 3, 2020Date of Patent: July 25, 2023Assignee: QUALCOMM INCORPORATEDInventors: Hyeokjin Lim, Bharani Chava, Foua Vang, Seung Hyuk Kang, Venugopal Boynapalli
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Patent number: 11437379Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.Type: GrantFiled: September 18, 2020Date of Patent: September 6, 2022Assignee: QUALCOMM IncorporatedInventors: Stanley Seungchul Song, Deepak Sharma, Bharani Chava, Hyeokjin Lim, Peijie Feng, Seung Hyuk Kang, Jonghae Kim, Periannan Chidambaram, Kern Rim, Giridhar Nallapati, Venugopal Boynapalli, Foua Vang
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Patent number: 11404374Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.Type: GrantFiled: September 30, 2020Date of Patent: August 2, 2022Assignee: QUALCOMM IncorporatedInventors: Hyeokjin Lim, Stanley Seungchul Song, Foua Vang, Seung Hyuk Kang
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Publication number: 20220115405Abstract: A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h1 and a first number of Mx layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h2 and a second number of Mx layer tracks that extend unidirectionally in the second direction, where h2>h1 and the second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of a height ratio hR=h2/h1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Inventors: Hyeokjin LIM, Venugopal BOYNAPALLI, Foua VANG, Seung Hyuk KANG
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Publication number: 20220102266Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Hyeokjin Lim, Stanley Seungchul Song, Foua Vang, Seung Hyuk Kang
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Patent number: 11290109Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.Type: GrantFiled: September 23, 2020Date of Patent: March 29, 2022Assignee: QUALCOMM INCORPORATEDInventors: Foua Vang, Hyeokjin Lim, Seung Hyuk Kang, Venugopal Boynapalli, Shitiz Arora
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Publication number: 20220094363Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Foua VANG, Hyeokjin LIM, Seung Hyuk KANG, Venugopal BOYNAPALLI, Shitiz ARORA
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Publication number: 20220093594Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Stanley Seungchul SONG, Deepak SHARMA, Bharani CHAVA, Hyeokjin LIM, Peijie FENG, Seung Hyuk KANG, Jonghae KIM, Periannan CHIDAMBARAM, Kern RIM, Giridhar NALLAPATI, Venugopal BOYNAPALLI, Foua VANG
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Patent number: 11133803Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: May 7, 2020Date of Patent: September 28, 2021Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
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Publication number: 20210280571Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2?m<PPG and PPG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell.Type: ApplicationFiled: March 3, 2020Publication date: September 9, 2021Inventors: Hyeokjin LIM, Bharani CHAVA, Foua VANG, Seung Hyuk KANG, Venugopal BOYNAPALLI
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Patent number: 10965289Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: GrantFiled: February 4, 2019Date of Patent: March 30, 2021Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta
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Publication number: 20210058076Abstract: A hybrid fin flip flop circuit may comprise a mixture of 1-fin transistors and multi-fin transistors. In one example, a flip flop circuit may comprise 1-fin transistors in at least one of the critical paths of the flip flop circuit such as the drive circuit, the input circuit, or the output circuit. In one example, a flip flop circuit may include: an input circuit; a clock driver circuit; an output circuit; and a latch circuit; wherein one of the input circuit, the clock driver circuit, or the output circuit comprises a multi-fin transistor and the latch circuit comprises a plurality of 1-fin transistors.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: Andi ZHAO, Ramaprasath VILANGUDIPITCHAI, Hyeokjin LIM, Seung Hyuk KANG
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Patent number: 10784345Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.Type: GrantFiled: February 4, 2020Date of Patent: September 22, 2020Assignee: QUALCOMM IncorporatedInventors: Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim
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Patent number: 10777640Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.Type: GrantFiled: February 4, 2020Date of Patent: September 15, 2020Assignee: QUALCOMM IncorporatedInventors: Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim
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Publication number: 20200266821Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.Type: ApplicationFiled: May 7, 2020Publication date: August 20, 2020Inventors: Satyanarayana SAHU, Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM, Mickael MALABRY, Mukul GUPTA
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Patent number: 10692808Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.Type: GrantFiled: September 18, 2017Date of Patent: June 23, 2020Assignee: QUALCOMM IncorporatedInventors: Renukprasad Hiremath, Hyeokjin Lim, Foua Vang, Xiangdong Chen, Venugopal Boynapalli
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Publication number: 20200176562Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Inventors: Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM
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Publication number: 20200176563Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Inventors: Xiangdong CHEN, Venugopal BOYNAPALLI, Hyeokjin LIM
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Patent number: 10605859Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.Type: GrantFiled: September 14, 2016Date of Patent: March 31, 2020Assignee: QUALCOMM IncorporatedInventors: Rami Salem, Lesly Zaren V. Endrinal, Hyeokjin Lim, Hadi Bunnalim, Robert Kim, Lavakumar Ranganathan, Mickael Malabry