Patents by Inventor Hyeok Jun CHOI
Hyeok Jun CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240194267Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.Type: ApplicationFiled: February 21, 2024Publication date: June 13, 2024Applicant: SK hynix Inc.Inventors: Hyeok Jun CHOI, Hee Sik PARK, Seung Geun JEONG
-
Publication number: 20240120616Abstract: A secondary battery includes an electrode assembly having a positive electrode provided with a positive electrode tab, a separator, and a negative electrode provided with a negative electrode tab, the positive electrode, the separator, and the negative electrode being wound, the electrode assembly having a core part at a center thereof; a can configured to receive the electrode assembly therein, the negative electrode tab being connected to the can; a cap assembly coupled to an opening of the can, the positive electrode tab being connected to the cap assembly; and a reinforcing member provided on an end of the separator exposed beyond the positive electrode or the negative electrode to prevent heat of the positive electrode tab or the negative electrode tab from being transferred to the separator.Type: ApplicationFiled: April 19, 2022Publication date: April 11, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Soon Kwan KWON, Su Taek JUNG, Seok Hoon JANG, Hyeok JEONG, Sang Ho BAE, Byeong Kyu LEE, Seong Won CHOI, Min Wook KIM, Yong Jun LEE
-
Patent number: 11942156Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.Type: GrantFiled: February 15, 2022Date of Patent: March 26, 2024Assignee: SK hynix Inc.Inventors: Hyeok Jun Choi, Hee Sik Park, Seung Geun Jeong
-
Publication number: 20230298645Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Hyeok Jun CHOI, Young Chul CHO, Seung Jin PARK, Jae Woo PARK, Young Don CHOI, Jung Hwan CHOI
-
Patent number: 11682436Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.Type: GrantFiled: July 14, 2021Date of Patent: June 20, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeok Jun Choi, Young Chul Cho, Seung Jin Park, Jae Woo Park, Young Don Choi, Jung Hwan Choi
-
Publication number: 20220383954Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.Type: ApplicationFiled: February 15, 2022Publication date: December 1, 2022Applicant: SK hynix Inc.Inventors: Hyeok Jun CHOI, Hee Sik PARK, Seung Geun JEONG
-
Publication number: 20220148634Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.Type: ApplicationFiled: July 14, 2021Publication date: May 12, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Hyeok Jun CHOI, Young Chul CHO, Seung Jin PARK, Jae Woo PARK, Young Don CHOI, Jung Hwan CHOI
-
Patent number: 11004864Abstract: A semiconductor device includes a stack structure including alternately stacked interlayer insulating layers and electrode patterns. The semiconductor device also includes a plurality of contact plugs connected to the electrode patterns. The semiconductor device further includes a supporting structure penetrating the stack structure between two adjacent contact plugs of the plurality of contact plugs, wherein the supporting structure has a cross section extending in a zigzag shape.Type: GrantFiled: September 4, 2019Date of Patent: May 11, 2021Assignee: SK hynix Inc.Inventors: Hyeok Jun Choi, Jun Yeong Hwang
-
Publication number: 20200258901Abstract: A semiconductor device includes a stack structure including alternately stacked interlayer insulating layers and electrode patterns. The semiconductor device also includes a plurality of contact plugs connected to the electrode patterns. The semiconductor device further includes a supporting structure penetrating the stack structure between two adjacent contact plugs of the plurality of contact plugs, wherein the supporting structure has a cross section extending in a zigzag shape.Type: ApplicationFiled: September 4, 2019Publication date: August 13, 2020Applicant: SK hynix Inc.Inventors: Hyeok Jun CHOI, Jun Yeong HWANG