Patents by Inventor Hyeok-Jun Son

Hyeok-Jun Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12342601
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: June 24, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Gyu Cho, Rak Hwan Kim, Hyeok-Jun Son, Do Sun Lee, Won Keun Chung
  • Publication number: 20250107136
    Abstract: Provided a semiconductor device. The semiconductor device comprises an active pattern extending in a first direction on a substrate, a gate stack extending in a second direction intersecting the first direction on the active pattern, and a source/drain pattern on at least one side of the gate stack, wherein the gate stack includes a first work function pattern, a second work function pattern on the first work function pattern, and a diffusion prevention pattern between the first work function pattern and the second work function pattern, and wherein a concentration of aluminum in the second work function pattern is greater than a concentration of aluminum in the first work function pattern.
    Type: Application
    Filed: April 5, 2024
    Publication date: March 27, 2025
    Inventors: Hyeok-Jun SON, Chan Hyeong LEE
  • Publication number: 20240128347
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Nam Gyu CHO, Rak Hwan KIM, Hyeok-Jun SON, Do Sun LEE, Won Keun CHUNG
  • Patent number: 11881519
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: January 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Gyu Cho, Rak Hwan Kim, Hyeok-Jun Son, Do Sun Lee, Won Keun Chung
  • Publication number: 20220285518
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Nam Gyu CHO, Rak Hwan KIM, Hyeok-Jun SON, Do Sun LEE, Won Keun CHUNG
  • Patent number: 11349007
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Gyu Cho, Rak Hwan Kim, Hyeok-Jun Son, Do Sun Lee, Won Keun Chung
  • Publication number: 20210210613
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Application
    Filed: September 9, 2020
    Publication date: July 8, 2021
    Inventors: Nam Gyu CHO, Rak Hwan KIM, Hyeok-Jun SON, Do Sun LEE, Won Keun CHUNG
  • Patent number: 10593670
    Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yeol Song, Wan-don Kim, Oh-seong Kwon, Hyeok-jun Son, Sang-jin Hyun, Hoon-joo Na
  • Patent number: 10312340
    Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-Don Kim, Oh-Seong Kwon, Hoon-Joo Na, Hyeok-Jun Son, Jae-Yeol Song, Sung-Kee Han, Sang-Jin Hyun
  • Patent number: 9991357
    Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeyeol Song, Wandon Kim, Hoonjoo Na, Suyoung Bae, Hyeok-Jun Son, Sangjin Hyun
  • Publication number: 20180019314
    Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.
    Type: Application
    Filed: September 27, 2017
    Publication date: January 18, 2018
    Inventors: Wan-Don Kim, Oh-Seong KWON, Hoon-Joo NA, Hyeok-Jun SON, Jae-Yeol SONG, Sung-Kee HAN, Sang-Jin HYUN
  • Publication number: 20180012889
    Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Inventors: Jae-Yeol Song, Wan-don Kim, Oh-seong Kwon, Hyeok-jun Son, Sang-jin Hyun, Hoon-joo NA
  • Patent number: 9806075
    Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Oh-seong Kwon, Hyeok-jun Son, Sang-jin Hyun, Hoon-joo Na
  • Patent number: 9793368
    Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeok-jun Son, Wan-don Kim, Hoon-joo Na, Sang-jin Hyun, Yoon-tae Hwang, Jae-yeol Song
  • Patent number: 9780183
    Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-Don Kim, Oh-Seong Kwon, Hoon-Joo Na, Hyeok-Jun Son, Jae-Yeol Song, Sung-Kee Han, Sang-Jin Hyun
  • Publication number: 20170005175
    Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may he between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.
    Type: Application
    Filed: June 20, 2016
    Publication date: January 5, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jaeyeol SONG, Wandon KIM, Hoonjoo NA, Suyoung BAE, Hyeok-Jun SON, Sangjin HYUN
  • Publication number: 20160315080
    Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.
    Type: Application
    Filed: January 20, 2016
    Publication date: October 27, 2016
    Inventors: Jae-yeol SONG, Wan-don KIM, Oh-seong KWON, Hyeok-jun SON, Sang-jin HYUN, Hoon-joo NA
  • Publication number: 20160315164
    Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.
    Type: Application
    Filed: February 19, 2016
    Publication date: October 27, 2016
    Inventors: Hyeok-jun Son, Wan-don Kim, Hoon-joo Na, Sang-jin Hyun, Yoon-tae Hwang, Jae-yeol Song
  • Publication number: 20160225868
    Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.
    Type: Application
    Filed: January 6, 2016
    Publication date: August 4, 2016
    Inventors: Wan-Don KIM, Oh-Seong KWON, Hoon-Joo NA, Hyeok-Jun SON, Jae-Yeol SONG, Sung-Kee HAN, Sang-Jin HYUN
  • Patent number: 9048307
    Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: June 2, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yeol Song, Jeong-Hee Han, Sang-Jin Hyun, Hyeok-Jun Son, Sung-Kee Han