Patents by Inventor Hyeokshin KWON

Hyeokshin KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363989
    Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyeong Lee, Hyeokshin Kwon, Jaeho Shin, Taehwan Jang, Insu Jeon
  • Patent number: 12062826
    Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyeong Lee, Hyeokshin Kwon, Jaeho Shin, Taehwan Jang, Insu Jeon
  • Publication number: 20240260485
    Abstract: A quantum processing device includes a first qubit chip including a first qubit device, a second qubit chip including a second qubit device, and a coupler configured to electrically connect the first qubit chip to the second qubit chip by using resonance.
    Type: Application
    Filed: January 26, 2024
    Publication date: August 1, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeokshin KWON, Jinhyoun KANG, Insu JEON
  • Patent number: 11812672
    Abstract: Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeokshin Kwon, Jaehyeong Lee, Insu Jeon
  • Publication number: 20230080023
    Abstract: A multi-mode resonator for a quantum computing element is included. In one general aspect, an apparatus including a multi-mode electromagnetic resonator includes a structure configured with a cavity therein that extends lengthwise in a first direction, the cavity including a first side surface and a second side surface facing each other, iris regions are at positions along the first direction on the first side surface of the cavity, the iris regions are arranged to overlap respective electromagnetic fields that form in the cavity in a target mode when electromagnetic energy is supplied to the cavity.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 16, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Taehwan JANG, Hyeokshin KWON, Jaeho SHIN
  • Patent number: 11574229
    Abstract: Provided is a three-dimensional (3D) transmon qubit apparatus including a body portion, a driver, a transmon element disposed in an internal space of the body portion, a first tunable cavity module disposed in the internal space of the body, and comprising a first superconductive metal panel; and a second tunable cavity module disposed in the internal space of the body, and comprising a second superconductive metal panel, wherein the transmon element is disposed between the first superconductive metal panel and the second superconductive metal panel; wherein the first tunable cavity module and the second tunable cavity module are configured to adjust a distance between the first superconductive metal panel and the second superconductive metal panel, and wherein the driver is configured to tune a resonance frequency by adjusting a 3D cavity by adjusting the distance between the first superconductive metal panel and the second superconductive metal panel.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehyeong Lee, Hyeokshin Kwon, Insu Jeon
  • Publication number: 20230004849
    Abstract: An active circulator includes: an active filter; and a power divider serially connected to the active filter, wherein three or more combinations of the active filter and the power divider are connected to form a loop.
    Type: Application
    Filed: March 1, 2022
    Publication date: January 5, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Taehwan JANG, Jinhyoun KANG, Hyeokshin KWON, Jaeho SHIN, Jaehyeong LEE, Insu JEON, Sungho HAN
  • Publication number: 20220271212
    Abstract: A multi-mode resonator is provided. The multi-mode resonator includes a housing and a cavity disposed in the housing, wherein the cavity includes a main cavity and a plurality of first subcavities disposed on a first lateral side of the main cavity.
    Type: Application
    Filed: December 20, 2021
    Publication date: August 25, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Taehwan Jang, Hyeokshin Kwon, Jaeho Shin, Jaehyeong Lee, Insu Jeon, Sungho Han
  • Patent number: 11349059
    Abstract: A Josephson junction device includes a planar arrangement including a first two-dimensional (2D) material layer, a graphene layer, and a second 2D material layer planarly arranged on a device substrate, the first 2D material layer including at least one layer of a 2D material, the graphene layer forming a first junction with the first 2D material layer, and the second 2D material layer forming a second junction with the graphene layer and including at least one layer of a 2D material. A distance between the first junction and the second junction is within a range configured to cause a Josephson effect.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehyeong Lee, Hyeokshin Kwon
  • Publication number: 20220149501
    Abstract: A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 12, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyeong LEE, Hyeokshin KWON, Jaeho SHIN, Taehwan JANG, Insu JEON
  • Patent number: 11245021
    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngtek Oh, Jinwook Jung, Hyeokshin Kwon, Wontaek Seo, Insu Jeon
  • Publication number: 20210328127
    Abstract: Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 21, 2021
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Hyeokshin KWON, Jaehyeong LEE, Insu JEON
  • Publication number: 20210217946
    Abstract: A Josephson junction device includes a planar arrangement including a first two-dimensional (2D) material layer, a graphene layer, and a second 2D material layer planarly arranged on a device substrate, the first 2D material layer including at least one layer of a 2D material, the graphene layer forming a first junction with the first 2D material layer, and the second 2D material layer forming a second junction with the graphene layer and including at least one layer of a 2D material. A distance between the first junction and the second junction is within a range configured to cause a Josephson effect.
    Type: Application
    Filed: September 9, 2020
    Publication date: July 15, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jaehyeong LEE, Hyeokshin KWON
  • Publication number: 20210216899
    Abstract: Provided is a three-dimensional (3D) transmon qubit apparatus including a body portion, a driver, a transmon element disposed in an internal space of the body portion, a first tunable cavity module disposed in the internal space of the body, and comprising a first superconductive metal panel; and a second tunable cavity module disposed in the internal space of the body, and comprising a second superconductive metal panel, wherein the transmon element is disposed between the first superconductive metal panel and the second superconductive metal panel; wherein the first tunable cavity module and the second tunable cavity module are configured to adjust a distance between the first superconductive metal panel and the second superconductive metal panel, and wherein the driver is configured to tune a resonance frequency by adjusting a 3D cavity by adjusting the distance between the first superconductive metal panel and the second superconductive metal panel.
    Type: Application
    Filed: June 30, 2020
    Publication date: July 15, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jaehyeong LEE, Hyeokshin KWON, Insu JEON
  • Publication number: 20210005731
    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Youngtek OH, Jinwook JUNG, Hyeokshin KWON, Wontaek SEO, Insu JEON
  • Patent number: 10818765
    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngtek Oh, Jinwook Jung, Hyeokshin Kwon, Wontaek Seo, Insu Jeon
  • Publication number: 20200135878
    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.
    Type: Application
    Filed: March 18, 2019
    Publication date: April 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Youngtek OH, Jinwook JUNG, Hyeokshin KWON, Wontaek SEO, lnsu JEON
  • Patent number: 9899473
    Abstract: Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer. The insulating layer may have a crystal structure. The insulating layer may include an insulating two-dimensional (2D) material. The insulating 2D material may include a hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer. The nanostructure may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngtek Oh, Hyeokshin Kwon, Hwansoo Suh, Insu Jeon
  • Patent number: 9882112
    Abstract: Multi-qubit devices and quantum computers including the same are provided. The multi-qubit device may include a first layer including a plurality of qubits; a second layer that is disposed on the first layer, and comprises a plurality of flux generating elements that apply flux to the plurality of qubits, a plurality of wire patterns that provide current to the plurality of flux generating elements, and a plurality of plugs that are disposed perpendicular to the plurality of flux generating elements and the plurality of wire patterns and interconnect the plurality of flux generating elements and the plurality of wire patterns. Each of the plurality of flux generating elements may be integrated with a corresponding one of the plurality of wire patterns and a corresponding one of the plurality of plugs.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeokshin Kwon, Youngtek Oh, Insu Jeon
  • Publication number: 20170186934
    Abstract: Multi-qubit devices and quantum computers including the same are provided. The multi-qubit device may include a first layer including a plurality of qubits; a second layer that is disposed on the first layer, and comprises a plurality of flux generating elements that apply flux to the plurality of qubits, a plurality of wire patterns that provide current to the plurality of flux generating elements, and a plurality of plugs that are disposed perpendicular to the plurality of flux generating elements and the plurality of wire patterns and interconnect the plurality of flux generating elements and the plurality of wire patterns. Each of the plurality of flux generating elements may be integrated with a corresponding one of the plurality of wire patterns and a corresponding one of the plurality of plugs.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 29, 2017
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeokshin KWON, Youngtek OH, Insu JEON