Patents by Inventor Hyeon-Cheon Seol
Hyeon-Cheon Seol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230031951Abstract: A memory device may include a data receiver configured to receive a plurality of read data chunks from a plurality of memory areas which transmit and receive data through one channel, a data compressor configured to generate a plurality of compressed data chunks from each of the plurality of read data chunks and a data output unit configured to simultaneously output the plurality of compressed data through the channel in response to a data output command.Type: ApplicationFiled: July 20, 2022Publication date: February 2, 2023Applicant: SK hynix Inc.Inventors: Hyeok Chan SOHN, Kang Wook JO, Hyeon Cheon SEOL, Byung Ryul KIM, Jae Young LEE
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Publication number: 20230030668Abstract: A storage device may include: a memory device for extracting bits having a first logic value among bits included in data received from outside the memory device, generating a plurality of compressed data chunks including the bits comprising the first logic value and position information representing positions of the bits having the first logic value in the data, and outputting the plurality of compressed data chunks in response to a data output command; and a memory controller for receiving the plurality of compressed data chunks from the memory device, and recovering the data, based on the bits having the first logic value, which are included in the plurality of compressed data, and the position information.Type: ApplicationFiled: July 18, 2022Publication date: February 2, 2023Applicant: SK hynix Inc.Inventors: Hyeok Chan SOHN, Kang Wook JO, Hyeon Cheon SEOL, Byung Ryul KIM, Jae Young LEE
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Patent number: 9054697Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.Type: GrantFiled: May 9, 2013Date of Patent: June 9, 2015Assignee: SK Hynix Inc.Inventors: Hae-Rang Choi, Yong-Ju Kim, Oh-Kyong Kwon, Kang-Sub Kwak, Jun-Yong Song, Hyeon-Cheon Seol
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Patent number: 9018991Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.Type: GrantFiled: December 15, 2013Date of Patent: April 28, 2015Assignees: SK Hynix Inc., Industry-University Cooperation Foundation Hanyang UniversityInventors: Hae-Rang Choi, Yong-Ju Kim, Oh-Kyong Kwon, Kang-Sub Kwak, Jun-Yong Song, Hyeon-Cheon Seol
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Publication number: 20150042387Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.Type: ApplicationFiled: December 15, 2013Publication date: February 12, 2015Applicants: Industry-University Cooperation Foundation Hanyang University, SK hynix Inc.Inventors: Hae-Rang CHOI, Yong-Ju KIM, Oh-Kyong KWON, Kang-Sub KWAK, Jun-Yong SONG, Hyeon-Cheon SEOL
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Publication number: 20130249593Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.Type: ApplicationFiled: May 9, 2013Publication date: September 26, 2013Applicant: SK hynix Inc.Inventors: Hae-Rang CHOI, Yong-Ju KIM, Oh-Kyong KWON, Kang-Sub KWAK, Jun-Yong SONG, Hyeon-Cheon SEOL
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Patent number: 8476924Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.Type: GrantFiled: December 22, 2011Date of Patent: July 2, 2013Assignees: Hynix Semiconductor Inc., Industry-University Cooperation Foundation Hanyang UniversityInventors: Hae-Rang Choi, Yong-Ju Kim, Oh-Kyong Kwon, Kang-Sub Kwak, Jun-Yong Song, Hyeon-Cheon Seol
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Publication number: 20130113518Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.Type: ApplicationFiled: December 22, 2011Publication date: May 9, 2013Inventors: Hae-Rang Choi, Yong-Ju Kim, Oh-Kyong Kwon, Kang-Sub Kwak, Jun-Yong Song, Hyeon-Cheon Seol