Patents by Inventor Hyeon-gyu You

Hyeon-gyu You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167090
    Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.
    Type: Application
    Filed: September 21, 2020
    Publication date: June 3, 2021
    Inventors: Ji Su YU, Jae-Ho PARK, Sanghoon BAEK, Hyeon Gyu YOU, Seung Young LEE, Seung Man LIM
  • Publication number: 20210165947
    Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.
    Type: Application
    Filed: November 3, 2020
    Publication date: June 3, 2021
    Inventors: JAE-HO PARK, SANGHOON BAEK, JI SU YU, HYEON GYU YOU, SEUNG YOUNG LEE, SEUNG MAN LIM, MIN JAE JEONG, JONG HOON JUNG
  • Publication number: 20210134837
    Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.
    Type: Application
    Filed: May 30, 2020
    Publication date: May 6, 2021
    Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
  • Publication number: 20210104611
    Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.
    Type: Application
    Filed: April 24, 2020
    Publication date: April 8, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji Su YU, Hyeon Gyu YOU, Seung Man LIM
  • Publication number: 20210013230
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho DO, Ji-Su YU, Hyeon-gyu YOU, Seung-Young LEE, Jae-boong LEE, Jong-hoon JUNG
  • Patent number: 10790305
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Ji-Su Yu, Hyeon-gyu You, Seung-Young Lee, Jae-Boong Lee, Jong-Hoon Jung
  • Publication number: 20200051977
    Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.
    Type: Application
    Filed: June 18, 2019
    Publication date: February 13, 2020
    Inventors: Jin-young Lim, Jae-ho Park, Sang-hoon Baek, Hyeon-gyu You, Dal-hee Lee
  • Publication number: 20190355750
    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 21, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Ji-Su Yu, Hyeon-gyu You, Seung-Young Lee, Jae-Boong Lee, Jong-Hoon Jung
  • Publication number: 20190355749
    Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.
    Type: Application
    Filed: March 5, 2019
    Publication date: November 21, 2019
    Inventors: Jung-ho Do, Ji-su Yu, Hyeon-gyu You, Seung-young Lee, Jae-boong Lee