Abstract: A semiconductor device may include a first bit line that extends in a first direction, a first active pillar and a second active pillar on the first bit line, a first gate insulating pattern enclosing the first active pillar, a second gate insulating pattern on the second active pillar, a first word line and a second word line that extends in a second direction that intersects the first direction, and a protection pattern between the first and second word lines. An air gap is between the first and second word lines and may be adjacent to the protection pattern.

Abstract: A nicotinamide adenine dinucleotide phosphate-dependent steroid dehydrogenase-like (NSDHL) inhibitor provided according to an aspect of the present invention can be used not only as an anticancer agent capable of overcoming resistance to EGFR-targeting anticancer agents, but also advantageously in the treatment of hyperlipidemia.

Abstract: Disclosed are a composite resin composition containing a thermosetting resin including an unsaturated polyester resin and a saturated polyester resin, a filler, and a processability-improving agent. More particularly, disclosed are a composite resin composition that is capable of providing a molded article having a lower specific gravity and improved surface quality compared to a conventional molded article by improving the compatibility and impregnability of a thermosetting resin and a filler using a processability-improving agent, and a molded article manufactured using the same.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: Disclosed is a thermosetting composite resin composition including a thermosetting resin, particularly an unsaturated polyester resin, a low-profile additive and an inorganic filler, and to a method of manufacturing an automobile shell plate using the same. The thermosetting composite resin composition can be used to manufacture not only automobile shell plates having low specific gravity and superior surface smoothness and mechanical properties but also structural parts such as interior parts for airplanes or railways.

Abstract: The present invention relates to a pharmaceutical composition comprising a DUSP1 inhibitor. The pharmaceutical composition comprising the DUSP1 inhibitor according to the present invention can solve the problems of inhibitors that target the active site because it inhibits DUSP1 by an allosteric inhibitory mechanism, and is effective for preventing or treating diseases involving DUSP1 enzymes, for example, a cancer such as a liver cancer, a breast cancer and a pancreatic cancer, a hepatitis C, and a depression. In particular, the DUSP1 inhibitor according to the present invention is very effective in treating a depression because it directly acts on neuronal growth.

Abstract: A nicotinamide adenine dinucleotide phosphate-dependent steroid dehydrogenase-like (NSDHL) inhibitor provided according to an aspect of the present invention can be used not only as an anticancer agent capable of overcoming resistance to EGFR-targeting anticancer agents, but also advantageously in the treatment of hyperlipidemia.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: Disclosed is a thermosetting composite resin composition including a thermosetting resin, particularly an unsaturated polyester resin, a low-profile additive and an inorganic filler, and to a method of manufacturing an automobile shell plate using the same. The thermosetting composite resin composition can be used to manufacture not only automobile shell plates having low specific gravity and superior surface smoothness and mechanical properties but also structural parts such as interior parts for airplanes or railways.

Abstract: The present invention relates to a pharmaceutical composition comprising a DUSP1 inhibitor. The pharmaceutical composition comprising the DUSP1 inhibitor according to the present invention can solve the problems of inhibitors that target the active site because it inhibits DUSP1 by an allosteric inhibitory mechanism, and is effective for preventing or treating diseases involving DUSP1 enzymes, for example, a cancer such as a liver cancer, a breast cancer and a pancreatic cancer, a hepatitis C, and a depression. In particular, the DUSP1 inhibitor according to the present invention is very effective in treating a depression because it directly acts on neuronal growth.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract: In a method of manufacturing a semiconductor device, a mask is formed on a substrate. The substrate is divided into a first region and a second region. An upper portion of the substrate in the first region is partially removed using the mask as an etching mask to form a recess. A first gate structure is formed in the recess. A portion of the mask in the first region is removed. A blocking layer pattern is formed on the substrate in the first region over the first gate structure.

Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.

Abstract: In a method of manufacturing a semiconductor device, a mask is formed on a substrate. The substrate is divided into a first region and a second region. An upper portion of the substrate in the first region is partially removed using the mask as an etching mask to form a recess. A first gate structure is formed in the recess. A portion of the mask in the first region is removed. A blocking layer pattern is formed on the substrate in the first region over the first gate structure.