Patents by Inventor Hyeon Kyu Lee
Hyeon Kyu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250199150Abstract: A system for processing radar data includes a radar device, at least one processor, and at least one memory including a computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to, acquire, from the radar device, first radar data corresponding to a target area and second radar data generated before the first radar data, convert at least a part of the second radar data based on a time difference between a time point at which the first radar data is acquired and a time point at which the second radar data is acquired, and generate refined data by considering the converted second radar data for trajectory processing along with the first radar data.Type: ApplicationFiled: December 28, 2023Publication date: June 19, 2025Applicant: BITSENSING INC.Inventors: Hyeon Kyu LEE, Yu Min HAN, Hee Mang SONG
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Publication number: 20250107070Abstract: A semiconductor device may include a first bit line that extends in a first direction, a first active pillar and a second active pillar on the first bit line, a first gate insulating pattern enclosing the first active pillar, a second gate insulating pattern on the second active pillar, a first word line and a second word line that extends in a second direction that intersects the first direction, and a protection pattern between the first and second word lines. An air gap is between the first and second word lines and may be adjacent to the protection pattern.Type: ApplicationFiled: February 13, 2024Publication date: March 27, 2025Inventors: HOSANG LEE, TAEJIN PARK, HYEON-KYU LEE, SUNG SOO YIM
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Patent number: 12221426Abstract: A nicotinamide adenine dinucleotide phosphate-dependent steroid dehydrogenase-like (NSDHL) inhibitor provided according to an aspect of the present invention can be used not only as an anticancer agent capable of overcoming resistance to EGFR-targeting anticancer agents, but also advantageously in the treatment of hyperlipidemia.Type: GrantFiled: August 29, 2019Date of Patent: February 11, 2025Assignees: Seoul National University R&DBFoundation, Korea Research Institute of Chemical Technology, National Cancer CenterInventors: Bong-Jin Lee, Kyu-Yeon Lee, Sang Jae Lee, Dong-Gyun Kim, Joo Youn Lee, Kwan-Young Jeong, Heui Cherl Yang, Hyeon-Kyu Lee, Hyoun Sook Kim
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Publication number: 20230082286Abstract: Disclosed are a composite resin composition containing a thermosetting resin including an unsaturated polyester resin and a saturated polyester resin, a filler, and a processability-improving agent. More particularly, disclosed are a composite resin composition that is capable of providing a molded article having a lower specific gravity and improved surface quality compared to a conventional molded article by improving the compatibility and impregnability of a thermosetting resin and a filler using a processability-improving agent, and a molded article manufactured using the same.Type: ApplicationFiled: September 7, 2022Publication date: March 16, 2023Inventors: Kyung Min Yu, Do Wan Lim, Gyu Nyeon Kim, Hyeon Kyu Lee
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Patent number: 11574912Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: GrantFiled: December 4, 2020Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
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Patent number: 11459441Abstract: Disclosed is a thermosetting composite resin composition including a thermosetting resin, particularly an unsaturated polyester resin, a low-profile additive and an inorganic filler, and to a method of manufacturing an automobile shell plate using the same. The thermosetting composite resin composition can be used to manufacture not only automobile shell plates having low specific gravity and superior surface smoothness and mechanical properties but also structural parts such as interior parts for airplanes or railways.Type: GrantFiled: September 11, 2019Date of Patent: October 4, 2022Assignees: Hyundai Motor Company, Kia Motors Corporation, Hanwha Q CELLS & Advanced Materials CorporationInventors: Sang Sun Park, Seong Muk Lee, Se Yong Kim, Ki Young Kim, Hyeon Kyu Lee
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Patent number: 11147807Abstract: The present invention relates to a pharmaceutical composition comprising a DUSP1 inhibitor. The pharmaceutical composition comprising the DUSP1 inhibitor according to the present invention can solve the problems of inhibitors that target the active site because it inhibits DUSP1 by an allosteric inhibitory mechanism, and is effective for preventing or treating diseases involving DUSP1 enzymes, for example, a cancer such as a liver cancer, a breast cancer and a pancreatic cancer, a hepatitis C, and a depression. In particular, the DUSP1 inhibitor according to the present invention is very effective in treating a depression because it directly acts on neuronal growth.Type: GrantFiled: February 28, 2018Date of Patent: October 19, 2021Assignees: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY, KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Seong Eon Ryu, Tae Hyun Park, Kwang Hwan Lee, Ju Seop Kang, Shin Hee Kim, Kyoung Tae Nam, Hyeon Kyu Lee
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Publication number: 20210253544Abstract: A nicotinamide adenine dinucleotide phosphate-dependent steroid dehydrogenase-like (NSDHL) inhibitor provided according to an aspect of the present invention can be used not only as an anticancer agent capable of overcoming resistance to EGFR-targeting anticancer agents, but also advantageously in the treatment of hyperlipidemia.Type: ApplicationFiled: August 29, 2019Publication date: August 19, 2021Inventors: Bong-Jin LEE, Kyu-Yeon LEE, Sang Jae LEE, Dong-Gyun KIM, Joo Youn LEE, Kwan-Young JEONG, Heui Cherl YANG, Hyeon-Kyu LEE, Hyoun Sook KIM
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Publication number: 20210091086Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo HONG, Young-Ju LEE, Joon-Yong CHOE, Jung-hyun KIM, Sang-jun LEE, Hyeon-Kyu LEE, Yoon-Chul CHO, Je-Min PARK, Hyo-Dong BAN
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Patent number: 10886277Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: GrantFiled: August 21, 2018Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
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Publication number: 20200377687Abstract: Disclosed is a thermosetting composite resin composition including a thermosetting resin, particularly an unsaturated polyester resin, a low-profile additive and an inorganic filler, and to a method of manufacturing an automobile shell plate using the same. The thermosetting composite resin composition can be used to manufacture not only automobile shell plates having low specific gravity and superior surface smoothness and mechanical properties but also structural parts such as interior parts for airplanes or railways.Type: ApplicationFiled: September 11, 2019Publication date: December 3, 2020Inventors: Sang Sun Park, Seong Muk Lee, Se Yong Kim, Ki Young Kim, Hyeon Kyu Lee
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Publication number: 20200155537Abstract: The present invention relates to a pharmaceutical composition comprising a DUSP1 inhibitor. The pharmaceutical composition comprising the DUSP1 inhibitor according to the present invention can solve the problems of inhibitors that target the active site because it inhibits DUSP1 by an allosteric inhibitory mechanism, and is effective for preventing or treating diseases involving DUSP1 enzymes, for example, a cancer such as a liver cancer, a breast cancer and a pancreatic cancer, a hepatitis C, and a depression. In particular, the DUSP1 inhibitor according to the present invention is very effective in treating a depression because it directly acts on neuronal growth.Type: ApplicationFiled: February 28, 2018Publication date: May 21, 2020Applicants: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY, KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGYInventors: Seong Eon RYU, Tae Hyun PARK, Kwang Hwan LEE, Ju Seop KANG, Shin Hee KIM, Kyoung Tae NAM, Hyeon Kyu LEE
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Publication number: 20190139963Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.Type: ApplicationFiled: August 21, 2018Publication date: May 9, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Augustin Jinwoo HONG, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
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Patent number: 9508649Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.Type: GrantFiled: January 8, 2016Date of Patent: November 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeon-Kyu Lee, Sunghee Han, Yoosang Hwang
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Publication number: 20160211215Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.Type: ApplicationFiled: January 8, 2016Publication date: July 21, 2016Inventors: Hyeon-Kyu Lee, Sunghee Han, Yoosang Hwang
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Patent number: 8946077Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.Type: GrantFiled: January 17, 2014Date of Patent: February 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeon-Kyu Lee, Bo-Young Song, Seung-Hee Ko, Jin-A Kim, Hyun-Gi Kim, Cheol-Ju Yun, Chae-Ho Lim
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Patent number: 8809993Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.Type: GrantFiled: February 21, 2013Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sei-lyn Kwak, Se-myeong Jang, Min-sung Kang, Yun-jae Lee, Hyeon-kyu Lee
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Publication number: 20140206186Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.Type: ApplicationFiled: January 17, 2014Publication date: July 24, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeon-Kyu Lee, Bo-Young Song, Seung-Hee Ko, Jin-A Kim, Hyun-Gi Kim, Cheol-Ju Yun, Chae-Ho Lim
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Patent number: 8669152Abstract: In a method of manufacturing a semiconductor device, a mask is formed on a substrate. The substrate is divided into a first region and a second region. An upper portion of the substrate in the first region is partially removed using the mask as an etching mask to form a recess. A first gate structure is formed in the recess. A portion of the mask in the first region is removed. A blocking layer pattern is formed on the substrate in the first region over the first gate structure.Type: GrantFiled: September 22, 2011Date of Patent: March 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-In Ryu, Jong-Un Kim, Hyeon-Kyu Lee
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Publication number: 20130241027Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.Type: ApplicationFiled: February 21, 2013Publication date: September 19, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Sei-lyn Kwak, Se-myeong Jang, Min-sung Kang, Yun-jae Lee, Hyeon-kyu Lee