Patents by Inventor Hyeon Kyun Noh
Hyeon Kyun Noh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11886783Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.Type: GrantFiled: January 12, 2023Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon Myung, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-Chul Park, Changwook Jeong
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Publication number: 20230142367Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.Type: ApplicationFiled: January 12, 2023Publication date: May 11, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon MYUNG, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-Chul Park, Changwook Jeong
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Patent number: 11574095Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.Type: GrantFiled: June 19, 2020Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon Myung, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-Chul Park, Changwook Jeong
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Patent number: 11282833Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.Type: GrantFiled: October 23, 2019Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Jin Lee, Ji Young Kim, Bong Soo Kim, Hyeon Kyun Noh, Moon Young Jeong
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Publication number: 20210158152Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.Type: ApplicationFiled: June 19, 2020Publication date: May 27, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghoon MYUNG, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-chul Park, Changwook Jeong
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Publication number: 20200203351Abstract: A memory device includes: a substrate including a first active region and a second active region spaced apart from each other; a device isolation film on the substrate, the device isolation film defining the first active region and the second active region; and a buried word line structure passing a low dielectric region between the first active region and the second active region, wherein the buried word line structure includes a gate electrode in a gate trench and a gate insulating layer between a portion of the gate electrode outside the low dielectric region and the gate trench, and wherein an air gap is disposed between a portion of the gate electrode within the low dielectric region and the gate trench.Type: ApplicationFiled: September 7, 2019Publication date: June 25, 2020Inventors: Kyo-suk CHAE, Tai-uk RIM, Hyeon-kyun NOH, Won-sok LEE
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Publication number: 20200161294Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.Type: ApplicationFiled: October 23, 2019Publication date: May 21, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dong Jin LEE, Ji Young KIM, Bong Soo KIM, Hyeon Kyun NOH, Moon Young JEONG
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Publication number: 20160086841Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.Type: ApplicationFiled: May 13, 2015Publication date: March 24, 2016Inventors: SEUNGHYUN SONG, Hyeon Kyun Noh, Taeyong Kwon, Sangsu Kim, Shigenobu Maeda, Krishna Bhuwalka, Uihui Kwon, Keunho Lee, Wonsok Lee