Patents by Inventor Hyeon Sang Shin

Hyeon Sang Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7468302
    Abstract: A method of forming a trench type isolation film of a semiconductor device, including the steps of sequentially forming a pad oxide film and a nitride film for a hard mask on a semiconductor substrate in which a cell region and a peri region are defined; patterning the nitride film using an etch process employing a cell array mask; coating a photoresist on the entire structure including the patterned nitride film; patterning the photoresist using a peri ISO mask; sequentially etching the nitride film, the pad oxide film, and the semiconductor substrate using the patterned photoresist as an etch mask, thereby forming first trenches; stripping the photoresist; etching the semiconductor substrate of the cell region and the peri region using the patterned nitride film as an etch mask, thereby forming second trenches in the cell region and third trenches, which are consecutive to the first trenches, in the peri region; and, forming an isolation film within the second and third trenches.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 23, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeon Sang Shin
  • Patent number: 6955957
    Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: October 18, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeon Sang Shin
  • Patent number: 6849503
    Abstract: To form metal interconnections in a flash memory device, the gate of the peripheral region is etched to form a first contact hole on a substrate. Silicon nitride and first oxide films are formed on the gate including the first contact hole. The first oxide film is etched to expose the source and filled by a first plug. A second oxide film is formed and etched with the first oxide films to form second contact holes exposing the drain, the source, and the first contact hole that are filled by second plugs. A third oxide film is formed and etched to form third contact holes exposing the first and second plugs and a portion of the second oxide film corresponding to the drain. The second and first oxide films are etched to form fourth contact holes exposing the first and second plugs and the drain. Metal interconnections fills the fourth contact holes.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: February 1, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeon Sang Shin
  • Publication number: 20040152251
    Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.
    Type: Application
    Filed: July 10, 2003
    Publication date: August 5, 2004
    Inventor: Hyeon Sang Shin
  • Patent number: 6465321
    Abstract: There is disclosed a method of forming a storage node in a semiconductor device capable of forming a storage node in a vertical structure, by forming a hard mask used to form a noble storage node using a TiN film deposited in a spacer shape on an oxide film and over the oxide film.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 15, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Hyeon Sang Shin, Chang Heon Park, Myung Pil Kim